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FUJITSU SEMICONDUCTOR DATA SHEET
Version 4.0
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90460/5 Series
MB90462/467/F462/F462A/F463A/V460
DESCRIPTION
The MB90460/5 series is a line of general-purpose, Fujitsu 16-bit microcontrollers designed for process control applications which require high-speed real-time processing, such as consumer products. While inheriting the AT architecture of the F2MC*1 family, the instruction set for the F2MC-16LX CPU core of the MB90460/5 series incorporates additional instructions for high-level languages, supports extended addressing modes, and contains enhanced multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions. In addition, the MB90460/5 series has an on-chip 32-bit accumulator which enables processing of long-word data. The peripheral resources integrated in the MB90460/5 series include: an 8/10-bit A/D converter, UARTs (SCI) 0 to 1, 16-bit PPG timer, multi-functional timer (16-bit free-running timer, input capture units (ICUs) 0 to 3, output compare units (OCUs) 0 and 5, 16-bit PPG timer, waveform generator), multi-pulse generator (16-bit PPG timer*2, 16-bit reload timer, waveform sequencer*2), PWC*2 0 to 1, 16-bit reload timer and DTP/external interrupt. Notes: *1: F2MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED. * 2: Multi-pulse generator and PWC 0 exist only in MB90460 series, ie, 16-bit PPG timer 1, waveform sequencer and PWC 0 are not present in MB90465 series (See section " BLOCK DIAGRAM").
FEATURES
* Minimum execution time: 62.5 ns / 4 MHz oscillation (uses PLL clock multiplication) maximum multiplier = 4 * Maximum memory space 16 Mbyte Linear/bank access (Continued)
PACKAGES
64-pin plastic QFP 64-pin plastic LQFP 64-pin plastic SH-DIP
(FPT-64P-M06)
(FPT-64P-M09)
(DIP-64P-M01)
MB90460/5 Series
(Continued) * Instruction set optimized for controller applications Supported data types : bit, byte, word, and long-word types Standard addressing modes : 23 types 32-bit accumulator enhancing high-precision operations Signed multiplication/division and extended RETI instructions * Enhanced high level language (C) and multi-tasking support instructions Use of a system stack pointer Symmetrical instruction set and barrel shift instructions * Program patch function (for two address pointers) * Enhanced execution speed : 4 byte instruction queue * Enhanced interrupt function Up to eight priority levels programmable External interrupt inputs : 8 lines * Automatic data transmission function independent of CPU operation Up to 16 channels for the extended intelligent I/O service DTP request inputs : 8 lines * Internal ROM FLASH : 64 Kbyte with flash security (MB90F462/F462A), 128Kbyte with flash security (MB90F463A) MASKROM : 64 Kbyte * Internal RAM EVA : 8 Kbyte FLASH : 2 Kbyte MASKROM : 2 Kbyte * General-purpose ports Up to 51 channels (input pull-up resistor settable for : 16 channels) * A/D Converter (RC) : 8 channels 8/10-bit resolution selectable Conversion time : Min. 6.13 s, 16 MHz operation * UART : 2 channels * 16-bit PPG : 3 channels (MB90460 series), 2 channels (MB90465 series) Mode switching function provided (PWM mode or one-shot mode) Can be worked with multi-functional timer, multi-pulse generator (MB90460 series only) or individually * 16-bit reload timer : 2 channels Can be worked with multi-pulse generator (MB90460 series only) or individually * 16-bit PWC timer : 2 channels (MB90460 series), 1 channel (MB90465 series) * Multi-functional timer Input capture : 4 channels Output compare with selectable buffer : 6 channels Free-running timer with up or up-down mode selection and selectable buffer: 1 channel 16-bit PPG : 1 channel Waveform generator : (16-bit timer : 3 channels, 3-phase waveform or dead time) * Multi-pulse generator 16-bit PPG : 1 channel (MB90460 series only) 16-bit reload timer : 1 channel Waveform sequencer : (16-bit timer with buffer and compare clear function) (MB90460 series only) * Timebase counter/watchdog timer : 18-bit (Continued)
2
MB90460/5 Series
(Continued) * Low-power consumption mode : Sleep mode Stop mode CPU intermittent operation mode * Package : LQFP-64 (FPT-64P-M09 : 0.65 mm pitch) QFP-64 (FPT-64P-M06 : 1.00 mm pitch) SDIP-64 (DIP-64P-M01 : 1.78 mm pitch) * CMOS technology
PRODUCT LINEUP
Part number MB90V460 Item Classification ROM size RAM size Development / evaluation product -- 8K Bytes Number of instruction Minimum execution time Addressing mode Data bit length Maximum memory space I/O port (CMOS) Pulse width counter timer PWC Mass-produced products (Flash ROM with flash security) 64K Bytes 128K Bytes 2K Bytes : 351 : 62.5 ns / 4 MHz (PLL x 4) : 23 : 1, 8, 16 bits : 16 MBytes : 51 : 2 channels 1 channel Mass-produced products (Mask ROM) 64K Bytes MB90F462 MB90F462A MB90F463A MB90462 MB90467
CPU function
I/O port
Timer function (select the counter timer from three internal clocks) Various pulse width measuring function (H pulse width, L pulse width, rising edge to falling edge period, falling edge to rising edge period, rising edge to rising edge period and falling edge to falling edge period) UART : 2 channels With full-duplex double buffer (8-bit length) Clock asynchronized or clock synchronized transmission (with start and stop bits) can be selectively used Transmission can be one-to-one (bidirectional commuication) or one-to-n (master-slave communication) Reload timer : 2 channels Reload mode, single-shot mode or event count mode selectable Can be worked with multi-pulse generator or individually (MB90460 series only) PPG timer : 3 channels 2 channels PWM mode or single-shot mode selectable Can be worked with multi-functional timer, multi-pulse generator (MB90460 series only) or individually
UART
16-bit reload timer
16-bit PPG timer
3
MB90460/5 Series
Part number MB90V460 Item Multi-functional timer (for AC/DC motor control) 16-bit free-running timer with up or up-down mode selection and buffer: 1 channel 16-bit output compare : 6 channels 16-bit input capture : 4 channels 16-bit PPG timer : 1 channel Waveform generator (16-bit timer: 3 channels, 3-phase waveform or dead time) Not present MB90F462 MB90F462A MB90F463A MB90462 MB90467
16-bit PPG timer : 1 channel Multi-pulse Waveform sequencer (includes 16-bit timer with buffer and compare clear funcgenerator tion) (for DC motor 16-bit reload timer operation (toggle output, one-shot output selectable) control) Event counter function : 1 channel built-in 8/10-bit A/D converter 8/10-bit resolution (8 channels) Conversion time : Min. 6.13 s (16 MHz internal clock) : Rising edge, falling edge, "L" level or "H" level
DTP/External 8 independent channels interrupt Selectable causes
Low-power Stop mode / Sleep mode / CPU intermittent operation mode consumption
Package
PGA256
LQFP-64 (FPT-64P-M09 : 0.65 mm pitch) QFP-64 (FPT-64P-M06 : 1.00 mm pitch) SDIP-64 (DIP-64P-M01 : 1.78 mm pitch) 4.5 V to 5.5 V* CMOS
Power supply voltage for operation* Process
* : Varies with conditions such as the operating frequency (See section " ELECTRICAL CHARACTERISTICS"). Assurance for the MB90V460 is given only for operation with a tool at a power supply voltage of 4.5 V to 5.5 V, an operating temperature of 0 to +25 C, and an operating frequency of 1 MHz to 16 MHz.
PACKAGE AND CORRESPONDING PRODUCTS
Package PGA256 FPT-64P-M09 FTP-64P-M06 DIP-64P-M01 : Available X : Not available Note: For more information about each package, see section " PACKAGE DIMENSIONS". X X X MB90V460 MB90F462 X MB90F462A MB90F463A X X MB90462 X MB90467 X
4
MB90460/5 Series
DIFFERENCES AMONG PRODUCTS
Memory Size In evaluation with an evaluation product, note the difference between the evaluation product and the product actually used. The following items must be taken into consideration. * The MB90V460 does not have an internal ROM, however, operations equivalent to chips with an internal ROM can be evaluated by using a dedicated development tool, enabling selection of ROM size by settings of the development tool. * In the MB90V460, images from FF4000H to FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH are mapped to bank FF only. (This setting can be changed by configuring the development tool.) * In the MB90462/467/F462/F462A/F463A, images from FF4000H to FFFFFFH are mapped to bank 00, and FF0000H to FF3FFFH are mapped to bank FF only. Difference between MB90460 series and MB90465 series * Waveform sequencer, 16-bit PPG timer 1, and PWC 0 are not present in MB90465 series. Difference between MB90F462, MB90F462A and MB90F463A * 64Kbytes flash ROM is avaliable in MB90F462 and MB90F462A while 128Kbytes flash ROM is avaliable in MB90F463A.
5
MB90460/5 Series
PIN ASSIGNMENT
P44/SNI1*2 P45/SNI2*2 P46/PPG2 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVCC AVR AVSS P60/SIN1 P61/SOT1 P62/SCK1 P63/INT7 MD0
64 63 62 61 60 59 58 57 56 55 54 53 52
P43/SNI0*2 P42/SCK0 P41/SOT0 P40/SIN0 P37/PPG0 P36/PPG1*2 C Vcc P35*1/RTO5 (Z) P34*1/RTO4 (W) P33*1/RTO3 (Y) P32*1/RTO2 (V) P31*1/RTO1 (X)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P30*1/RTO0 (U) VSS P27/IN3 P26/IN2 P25/IN1 P24/IN0 P23/PWO1 P22/PWI1 P21/TO1 P20/TIN1 P17/FRCK P16/INT6/TO0 P15/INT5/TIN0 P14/INT4 P13/INT3 P12/INT2/DTTI1*2 P11/INT1 P10/INT0/DTTI0 P07/PWO0*2
QFP-64 (TOP VIEW) (FPT-64P-M06)
*1: Heavy current pins *2: Resource function for these pins are not applicable to MB90465 series
RSTX MD1 MD2 X0 X1 VSS P00*1/OPT0*2 P01*1/OPT1*2 P02*1/OPT2*2 P03*1/OPT3*2 P04*1/OPT4*2 P05*1/OPT5*2 P06*1/PWI0*2
20 21 22 23 24 25 26 27 28 29 30 31 32
(Continued)
6
MB90460/5 Series
(Continued)
P45/SNI2*2 P46/PPG2 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVCC AVR AVSS P60/SIN1 P61/SOT1 P62/SCK1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P44/SNI1*2 P43/SNI0*2 P42/SCK0 P41/SOT0 P40/SIN0 P37/PPG0 P36/PPG1*2 C Vcc P35*1/RTO5 (Z) P34*1/RTO4 (W) P33*1/RTO3 (Y) P32*1/RTO2 (V) P31*1/RTO1 (X) P30*1/RTO0 (U) VSS
LQFP-64 (TOP VIEW) (FPT-64P-M09)
P27/IN3 P26/IN2 P25/IN1 P24/IN0 P23/PWO1 P22/PWI1 P21/TO1 P20/TIN1 P17/FRCK P16/INT6/TO0 P15/INT5/TIN0 P14/INT4 P13/INT3 P12/INT2/DTTI1*2 P11/INT1 P10/INT0/DTTI0
*1: Heavy current pins *2: Resource function for these pins are not applicable to MB90465 series
P63/INT7 MD0 RSTX MD1 MD2 X0 X1 VSS P00*1/OPT0*2 P01*1/OPT1*2 P02*1/OPT2*2 P03*1/OPT3*2 P04*1/OPT4*2 P05*1/OPT5*2 P06/PWI0*2 P07/PWO0*2
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
(Continued)
7
MB90460/5 Series
(Continued)
C P36/PPG1*2 P37/PPG0 P40/SIN0 P41/SOT0 P42/SCK0 P43/SNI0*2 P44/SNI1*2 P45/SNI2*2 P46/PPG2 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVCC AVR AVSS P60/SIN1 P61/SOT1 P62/SCK1 P63/INT7 MD0 RSTX MD1 MD2 X0 X1 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
SDIP-64 (TOP VIEW) (DIP-64P-M01)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
Vcc P35*1/RTO5 (Z) P34*1/RTO4 (W) P33*1/RTO3 (Y) P32*1/RTO2 (V) P31*1/RTO1 (X) P30*1/RTO0 (U) VSS P27/IN3 P26/IN2 P25/IN1 P24/IN0 P23/PWO1 P22/PWI1 P21/TO1 P20/TIN1 P17/FRCK P16/INT6/TO0 P15/INT5/TIN0 P14/INT4 P13/INT3 P12/INT2/DTTI1*2 P11/INT1 P10/INT0/DTTI0 P07/PWO0*2 P06/PWI0*2 P05*1/OPT5*2 P04*1/OPT4*2 P03*1/OPT3*2 P02*1/OPT2*2 P01*1/OPT1*2 P00*1/OPT0*2
*1: Heavy current pins *2: Resource function for these pins are not applicable to MB90465 series
8
MB90460/5 Series
PIN DESCRIPTION
Pin no. LQFPM09*1 22,23 19 QFPM06*2 23,24 20 SDIP*3 30,31 27 Pin name X0,X1 RSTX P00 ~ P05 25~30 26~31 33~38 OPT0 ~ OPT5*4 P06 PWI0*4 P07 PWO0*4 P10 INT0 33 34~35 41~42 DTTI0 P11 34 35 42 INT1 P12 INT2 35 36 43 DTTI1*4 P13 ~ P14 36~37 37~38 44~45 INT3 ~ INT4 P15 38 39 46 INT5 TIN0 P16 39 40 47 INT6 TO0 40 41 48 P17 FRCK P20 TIN1 C C C C C Port input C C D I/O circuit A B Pin status during reset Oscillating Oscillation input pins.
Function
Reset input External reset input pin. General-purpose I/O ports. Output terminals OPT0~5 of the waveform sequencer. These pins output the waveforms specified at the output data registers of the waveform sequencer circuit. Output is generated when OPE0~5 of OPCR is enabled. General-purpose I/O ports. PWC 0 signal input pin. General-purpose I/O ports. PWC 0 signal output pin. General-purpose I/O ports. Can be used as interrupt request input channels 0. Input is enabled when 1 is set in EN0 in standby mode. RTO0~5 pins for fixed-level input. This function is enabled when the waveform generator enables its input bits. General-purpose I/O ports. Can be used as interrupt request input channels 1. Input is enabled when 1 is set in EN1 in standby mode. General-purpose I/O ports. Can be used as interrupt request input channels 2. Input is enabled when 1 is set in EN2 in standby mode. OPT0~5 pins for fixed-level input. This function is enabled when the waveform sequencer enables its input bit. General-purpose I/O ports. Can be used as interrupt request input channels 3 to 4. Input is enabled when 1 is set in EN3 to EN4 in standby mode. General-purpose I/O ports. Can be used as interrupt request input channel 5. Input is enabled when 1 is set in EN5 in standby mode. External clock input pin for reload timer 0. General-purpose I/O ports. Can be used as interrupt request input channels 6. Input is enabled when 1 is set in EN6 in standby mode. Event output pin for reload timer 0. General-purpose I/O ports. External clock input pin for free-running timer. General-purpose I/O ports. External clock input pin for reload timer 1.
31
32
39
E
32
33
40
E
41
42
49
F
9
MB90460/5 Series
Pin no. LQFPM09*1 42 QFPM06*2 43 SDIP*3 50 Pin name P21 TO1 P22 PWI1 P23 PWO1 P24 ~ P27 45~48 46~49 53~56 F I/O circuit Pin status during reset
Function General-purpose I/O ports. Event output pin for reload timer 1. General-purpose I/O ports. PWC 1 signal input pin. General-purpose I/O ports. PWC 1 signal output pin. General-purpose I/O ports. Trigger input pins for input capture channels 0 to 3. When input capture channels 0 to 3 are used for input operation, these pins are enabled as required and must not be used for any other I/P. General-purpose I/O ports.
F
43
44
51
F
44
45
52
F
IN0 ~ IN3
P30 ~ P35 50~55 51~56 58~63 RTO0 ~ RTO5 P36 ~ 37 58~59 59~60 2~3 PPG1* , PPG0 P40 60 61 4 F Port input P41 61 62 5 SOT0 P42 62 63 6 SCK0 P43 63 64 7 F F F
4
G
Waveform generator output pins. These pins output the waveforms specified at the waveform generator. Output is generated when waveform generator output is enabled. General-purpose I/O ports.
H
Output pins for PPG channels 1, 0. This function is enabled when PPG channels 1, 0 enable output. General-purpose I/O ports. Serial data input pin for UART channel 0. While UART channel 0 is operating for input, the input of this pin is used as required and must not be used for any other input. General-purpose I/O ports. Serial data output pin for UART channel 0. This function is enabled when UART channel 0 enables data output. General-purpose I/O ports. Serial clock I/O pin for UART channel 0. This function is enabled when UART channel 0 enables clock output. General-purpose I/O ports. Trigger input pins for position detection of the waveform sequencer. When this pin is used for input operation, it is enabled as required and must not be used for any other I/P. General-purpose I/O ports.
SIN0
SNI0*4
P44 64 1 8 F
SNI1*
4
Trigger input pins for position detection of the Multi-pulse generator. When this pin is used for input operation, it is enabled as required and must not be used for any other I/P. General-purpose I/O ports.
P45 1 2 9 F
SNI2*4
Trigger input pins for position detection of the Multi-pulse generator. When this pin is used for input operation, it is enabled as required and must not be used for any other I/P. General-purpose I/O ports.
P46 2 3 10 PPG2 F
Output pins for PPG channel 2. This function is enabled when PPG channel 2 enables output.
10
MB90460/5 Series
Pin no. LQFPM09*1 3~10 11 12 13 QFPM06*2 4~11 12 13 14 SDIP*3 Pin name P50 ~ P57 11~18 19 20 21 AN0 ~ AN7 AVCC AVR AVSS P60 14 15 22 F I J K J Power input I/O circuit Pin status during reset
Function General-purpose I/O ports.
Analog input A/D converter analog input pins. This function is enabled when the analog input specification is enabled (ADER). Vcc power input pin for analog circuits. Vref+ input pin for the A/D converter. This voltage must not exceed AVcc. Vref- is fixed to AVss. Vss power input pin for analog circuits. General-purpose I/O ports. Serial data input pin for UART channel 1. While UART channel 1 is operating for input, the input of this pin is used as required and must not be used for any other input. General-purpose I/O ports.
SIN1
P61 15 16 23 SOT1 P62 16 17 24 SCK1 P63 17 18 25 INT7 MD0 MD1,MD2 Vss Vcc F F F Port Input
Serial data output pin for UART channel 1. This function is enabled when UART channel 1 enables data output. General-purpose I/O port. Serial clock I/O pin for UART channel 1. This function is enabled when UART channel 1 enables clock output. General-purpose I/O port. Usable as interrupt request input channel 7. Input is enabled when 1 is set in EN7 in standby mode. Input pin for operation mode specification. Connect this pin directly to Vcc or Vss. Input pin for operation mode specification. Connect this pin directly to Vcc or Vss. Power (0 V) input pin. Power (5 V) input pin.
18 20,21 24,49 56
19 21,22 25,50 57
26 28,29 32,57 64
L Mode input L - - Power input
*1: FPT-64P-M09 *2: FPT-64P-M06 *3: DIP-64P-M01 *4: Pin names not applicable to MB90465 series
11
MB90460/5 Series
I/O CIRCUIT TYPE
Classification
X1 N-ch P-ch Xout P-ch N-ch Standby mode control
Type
Remarks
A
X0
Main clock (main clock crystal oscillator) * At an oscillation feedback resistor of approximately 1 M
B
R
* Hysteresis input * Resistor approximately 50 k
R
P-ch
Pull-up control P-ch Pout Nout
C
N-ch
* CMOS output * Hysteresis input * Selectable pull-up resistor approximately 50 k * IOL = 4 mA
Hysteresis input Standby mode control
R
P-ch
Pull-up control P-ch Pout Nout
D
N-ch
* CMOS output * CMOS input * Selectable pull-up resistor approximately 50 k * IOL = 12 mA
CMOS input Standby mode control
R
P-ch
Pull-up control P-ch Pout Nout
E
N-ch
* CMOS output * CMOS input * Selectable pull-up resistor approximately 50 k * IOL = 4 mA
CMOS input Standby mode control
12
MB90460/5 Series
Classification
P-ch
Type
Remarks
Pout Nout
F
N-ch
* CMOS output * Hysteresis input * IOL = 4 mA
Hysteresis input Standby mode control
P-ch
Pout Nout
G
N-ch
* CMOS output * CMOS input * IOL = 12 mA
CMOS input Standby mode control
P-ch
Pout Nout
H
N-ch
* CMOS output * CMOS input * IOL = 4 mA
CMOS input Standby mode control
P-ch
Pout Nout
I
N-ch
CMOS input Analog input control Analog input
* * * *
CMOS output CMOS input
Analog input IOL = 4 mA
P-ch
J
N-ch
IN
* Power supply input protection circuit
13
MB90460/5 Series
Classification Type Remarks
P-ch
Analog input enable IN
K
N-ch
* A/D converter reference voltage (AVR) input pin with protection circuit
Analog input enable
L
* Hysteresis input
14
MB90460/5 Series
HANDLING DEVICES
1. Preventing latch-up
CMOS ICs may cause latch-up in the following situations: * When a voltage higher than VCC or lower than VSS is applied to input or output pins. * When a voltage exceeding the rating is applied between VCC and VSS. * When AVCC power is supplied prior to the VCC voltage. If latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the device. Use meticulous care not to let it occur. For the same reason, also be careful not to let the analog power-supply voltage exceed the digital power-supply voltage.
2. Handling unused input pins
Unused input pins left open may cause abnormal operation, or latch-up leading to permanent damage. Unused input pins should be pulled up or pulled down through at least 2 k resistance. Unused input/output pins may be left open in output state, but if such pins are in input state they should be handled in the same way as input pins.
3. Use of the external clock
When the device uses an external clock, drive only the X0 pin while leaving the X1 pin open (See the illustration below). MB90460/5 series
X0
Open
X1
4. Power supply pins (VCC/VSS)
In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to avoid abnormal operations including latch-up. However, connect the pins external power and ground lines to lower the electro-magnetic emission level to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. Make sure to connect VCC and VSS pins via lowest impedance to power lines. It is recommended to provide a bypass capacitor of around 0.1 F between VCC and VSS pin near the device.
5. Crystal oscillator circuit
Noise around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits. It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with an ground area for stabilizing the operation.
6. Turning-on sequence of power supply to A/D converter and analog inputs
Make sure to turn on the A/D converter power supply (AVCC, AVSS, AVR) and analog inputs (AN0 to AN7) after turning-on the digital power supply (VCC). Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that the voltage of AVR dose not exceed AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable). 15
MB90460/5 Series
7. Connection of unused pins of A/D converter
Connect unused pin of A/D converter to AVCC = VCC, AVSS = AVR = VSS.
8. N.C. pin
The N.C. (internally connected) pin must be opened for use.
9. Notes on energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 s or more.
10. Initialization
In the device, there are internal registers which are initialized only by a power-on reset. To initialize these registers turning on the power again.
11. Return from standby state
If the power supply voltage goes below the standby RAM holding voltage in the standby state, the device may fail to return from the standby state. In this case, reset the device via the external reset pin to return to the normal state.
16
MB90460/5 Series
BLOCK DIAGRAM
X0 X1
Clock control circuit Reset circuit (Watchdog timer) Interrupt controller
CPU
F2MC-16LX series core
Other pins Vss x 2, Vcc x 1, MD0-2, C
RSTX
Timebase timer Delayed interrupt generator Multi-functional timer 16-bit PPG (Ch0)
P37/PPG0
P11/INT1 P13/INT3 to P14/INT4 P40/SIN0 P41/SOT0 P42/SCK0
2 8
DTP/External interrupt UART (Ch0) Multi-pulse generator
16-bit input capture (Ch0/1/2/3) 16-bit free-running timer 16-bit output compare (Ch0~5)
4
4
P24/IN0 to P27/IN3
P17/FRCK P30/RTO0 (U) P31/RTO1 (X) P32/RTO2 (V) P33/RTO3 (Y) P34/RTO4 (W) P35/RTO5 (Z) P10/INT0/DTTI0
P36/PPG1*1 P16/INT6/TO0 P15/INT5/TIN0 P43/SNI0*1 to P45/SNI2*1 P00/OPT0*1 P01/OPT1*1 P02/OPT2*1 P03/OPT3*1 P04/OPT4*1 P05/OPT5*1 P12/INT2/ DTTI1*1 P06/PWI0*1 P07/PWO0*1 P46/PPG2
3 3
16-bit PPG*2 (Ch1) 16-bit reload timer (Ch0)
F2MC-16LX bus
Waveform generator 16-bit reload timer (Ch1) PWC (Ch1)
Waveform*2 sequencer
P20/TIN1 P21/TO1 P22/PWI1 P23/PWO1 P60/SIN1 P61/SOT1 P62/SCK1 P63/INT7
PWC*2 (Ch0) 16-bit PPG (Ch2) CMOS I/O port 0, 1, 3, 4
UART (Ch1) CMOS I/O port 1, 2, 3, 6 CMOS I/O port 5
RAM ROM
ROM correction ROM mirroring
Note: P00 to P07 (8 channels): With registers that can be used as input pull-up resistors P10 to P17 (8 channels): With registers that can be used as input pull-up resistors *1: Resource function for these pins are not applicable to MB90465 series *2: Not present in MB90465 series
A/D converter (8/10 bit)
8
P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7
AVCC AVR AVSS
17
MB90460/5 Series
MEMORY MAP
FFFFFFH
ROM area
Address #1
FC0000H
010000H
ROM area
Address #2 (FF bank image)
: Internal access memory : Access not allowed
004000H 003FE0H Address #3 RAM area
Register
Peripheral area
000100H 0000C0H 000000H
Peripheral area In Single chip mode the mirror function is support
Parts no. MB90462 MB90467 MB90F462 MB90F462A MB90F463A MB90V460
Address#1 FF0000H FF0000H FF0000H FF0000H FE0000H (FF0000H)
Address#2 004000H 004000H 004000H 004000H 004000H 004000H
Address#3 000900H 000900H 000900H 000900H 000900H 002100H
Note: The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C compiler small model. The lower 16-bit is assigned to the same address, enabling reference of the table on the ROM without stating "far". For example, if an attempt has been made to access 00C000H, the contents of the ROM at FFC000H are accessed actually. Since the ROM area of the FF bank exceeds 48 Kbytes, the whole area cannot be reflected in the image for the 00 bank. The ROM data at FF4000H to FFFFFFH looks, therefore, as if it were the image for 004000H to 00FFFFH. Thus, it is recommended that the ROM data table be stored in the area of FF4000H to FFFFFFH.
18
MB90460/5 Series
F2MC-16LX CPU PROGRAMMING MODEL
* Dedicated registers
AH
AL
USP
: Accumlator (A) Dual 16-bit register used for storing results of calculation etc. The two 16-bit registers can be combined to be used as a 32-bit register. : User stack pointer (USP) The 16-bit pointer indicating a user stack address. : System stack pointer (SSP) The 16-bit pointer indicating the status of the system stack address. : Processor status (PS) The 16-bit register indicating the system status. : Program counter (PC) The 16-bit register indicating storing location of the current instruction code. : Direct page register (DPR) The 8-bit register indicating bit 8 through 15 of the operand address in the short direct addressing mode. : Program bank register (PCB) The 8-bit register indicating the program space. : Data bank register (DTB) The 8-bit register indicating the data space. : User stack bank register (USB) The 8-bit register indicating the user stack space. : System stack bank register (SSB) The 8-bit register indicating the system stack space. : Additional data bank register (ADB) The 8-bit register indicating the additional data space.
SSP
PS
PC
DPR
PCB
DTB
USB
SSB
ADB
8 bit 16 bit 32 bit
19
MB90460/5 Series
* General-purpose registers
Maximum of 32 banks
R7 R5 R3 R1 RW3
R6 R4 R2 R0
RW7 RL3 RW6 RW5 RL2 RW4
RL1 RW2 RW1 RL0 000180H + (RP x 10H) RW0 16 bit
* Processor status (PS)
ILM
RP
CCR
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PS Initial value X ILM2 ILM1 ILM0 0 0 0 B4 0 B3 0 B2 0 B1 0 B0 0 I 0 S 1 T X N X Z X V X C X
: Unused : Undefined
20
MB90460/5 Series
I/O MAP
MB90460/5 series I/O map
Address
000000H 000001H 000002H 000003H 000004H 000005H 000006H 000007H 000008H 000009H 00000AH 00000BH 00000CH 00000DH ~ 0FH 000010H 000011H 000012H 000013H 000014H 000015H 000016H 000017H 000018H 000019H 00001AH 00001BH 00001CH 00001DH 00001EH ~ 1FH 000020H 000021H 000022H 000023H 000024H 000025H 000026H 000027H SMR0 SCR0 Serial mode register 0 Serial control register 0 CDCR1 RDR0 RDR1 Clock division control register 1 Port 0 pull-up resistor setting register Port 1 pull-up resistor setting register CDCR0 Clock division control register 0 DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 ADER Port 0 direction register Port 1 direction register Port 2 direction register Port 3 direction register Port 4 direction register Port 5 direction register Port 6 direction register Analog input enable register PWCSL0 PWCSH0 PWC0 DIV0 PWC control status register CH0
Abbreviation
PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6
Register
Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register
Byte Word access access
R/W R/W R/W R/W R/W R/W R/W Prohibited area R/W R/W R/W Prohibited area R/W R/W R/W R/W R/W R/W R/W R/W Prohibited area R/W Prohibited area R/W R/W R/W Prohibited area R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Resource name
Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6
Initial value
XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB -XXXXXXXB XXXXXXXXB ----XXXXB
00000000B 00000000B PWC timer (CH0)* XXXXXXXXB XXXXXXXXB ------00B
PWC data buffer register CH0 Divide ratio control register CH0
Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 5, A/D
00000000B 00000000B 00000000B 00000000B -0000000B 00000000B ----0000B 11111111B
Communication prescaler 0
0---0000B
Communication prescaler 1 Port 0 Port 1
0---0000B 00000000B 00000000B
00000000B UART0 00000100B XXXXXXXXB 00001000B 00000000B UART1 00000100B XXXXXXXXB 00001000B
SIDR0 / SODR0 Input data register 0 / Output data register 0 SSR0 SMR1 SCR1 Serial status register 0 Serial mode register 1 Serial control register 1
SIDR1 / SODR1 Input data register 1 / Output data register 1 SSR1 Status register 1
21
MB90460/5 Series
MB90460/5 series I/O map
Address
000028H 000029H 00002AH 00002BH 00002CH 00002DH ~ 2FH 000030H 000031H 000032H 000033H 000034H 000035H 000036H 000037H 000038H 000039H 00003AH 00003BH 00003CH 00003DH 00003EH 00003FH 000040H 000041H 000042H 000043H 000044H 000045H 000046H 000047H 000048H 000049H 00004AH 00004BH 00004CH 00004DH 00004EH 00004FH ENIR EIRR ELVRL ELVRH ADCS0 ADCS1 ADCR0 ADCR1 PDCR0 Interrupt / DTP enable register Interrupt / DTP cause register Request level setting register (lower byte) Request level setting register (higher byte) A/D control status register 0 A/D control status register 1 A/D data register 0 A/D data register 1 PPG0 down counter register
Abbreviation
PWCSL1 PWCSH1 PWC1 DIV1
Register
PWC control status register CH1
Byte Word access access
R/W R/W R/W Prohibited area R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R R/W R R/W R/W R/W R/W
Resource name
Initial value
00000000B 00000000B
PWC data buffer register CH1 Divide ratio control register CH1
PWC timer (CH1)
XXXXXXXXB XXXXXXXXB ------00B
00000000B DTP/external interrupt XXXXXXXXB 00000000B 00000000B 00000000B 8/10-bit A/D converter 00000000B XXXXXXXXB 00000-XXB 11111111B 11111111B XXXXXXXXB 16-bit PPG timer (CH0) XXXXXXXXB XXXXXXXXB XXXXXXXXB --000000B 00000000B 11111111B 11111111B XXXXXXXXB 16-bit PPG timer (CH1)* XXXXXXXXB XXXXXXXXB XXXXXXXXB --000000B 00000000B 11111111B 11111111B XXXXXXXXB 16-bit PPG timer (CH2) XXXXXXXXB XXXXXXXXB XXXXXXXXB --000000B 00000000B
PCSR0
PPG0 period setting register
-
W
PDUT0 PCNTL0 PCNTH0 PDCR1
PPG0 duty setting register
R/W R/W -
W R/W R/W R
PPG0 control status register
PPG1 down counter register
PCSR1
PPG1 period setting register
-
W
PDUT1 PCNTL1 PCNTH1 PDCR2
PPG1 duty setting register
R/W R/W -
W R/W R/W R
PPG1 control status register
PPG2 down counter register
PCSR2
PPG2 period setting register
-
W
PDUT2 PCNTL2 PCNTH2
PPG2 duty setting register
R/W R/W
W R/W R/W
PPG2 control status register
22
MB90460/5 Series
MB90460/5 series I/O map
Address
000050H 000051H 000052H 000053H 000054H 000055H 000056H 000057H 000058H 000059H 00005AH 00005BH 00005CH 00005DH 00005EH 00005FH 000060H 000061H 000062H 000063H 000064H 000065H 000066H 000067H 000068H 000069H 00006AH 00006BH 00006CH ~ 6EH 00006FH ROMM
Abbreviation
TMRR0
Register
16-bit timer register 0
Byte Word access access
R/W
Resource name
Initial value
XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
TMRR1
16-bit timer register 1
-
R/W
TMRR2 DTCR0 DTCR1 DTCR2 SIGCR CPCLRB / CPCLR TCDT TCCSL TCCSH IPCP0
16-bit timer register 2 16-bit timer control register 0 16-bit timer control register 1 16-bit timer control register 2 Waveform control register Compare clear buffer register / Compare clear register (lower) Timer data register (lower) Timer control status register (lower) Timer control status register (upper) Input capture data register CH0
R/W R/W R/W R/W -
R/W R/W R/W R/W R/W R/W
Waveform generator
XXXXXXXXB XXXXXXXXB 00000000B 00000000B 00000000B 00000000B 11111111B 11111111B
R/W R/W -
R/W R/W R/W R
16-bit free-running timer
00000000B 00000000B 00000000B -0000000B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
IPCP1
Input capture data register CH1
-
R
IPCP2
Input capture data register CH2
-
R
IPCP3 PICSL01 PICSH01 ICSL23 ICSH23
Input capture data register CH3 Input capture control status register 01 (lower) PPG output control / Input capture control status register 01 (upper) Input capture control status register 23 (lower) Input capture control status register 23 (upper)
R/W R/W R/W R
R R/W R/W R/W R
16-bit input capture (CH0 ~ CH3)
XXXXXXXXB 00000000B 00000000B 00000000B ------00B
Prohibited area ROM mirroring function selection register W W ROM mirroring function -------1B
23
MB90460/5 Series
MB90460/5 series I/O map
Address
000070H 000071H 000072H 000073H 000074H 000075H 000076H 000077H 000078H 000079H 00007AH 00007BH 00007CH 00007DH 00007EH 00007FH 000080H 000081H 000082H 000083H 000084H 000085H 000086H 000087H 000088H 000089H 00008AH 00008BH 00008CH 00008DH 00008EH 00008FH 000090H ~ 9DH 00009EH 00009FH 0000A0H 0000A1H 0000A2H ~ A7H 0000A8H 0000A9H WDTC TBTC Watchdog control register Timebase timer control register PACSR DIRR LPMCR CKSCR
Abbreviation
OCCPB0 / OCCP0 OCCPB1 / OCCP1 OCCPB2 / OCCP2 OCCPB3 / OCCP3 OCCPB4 / OCCP4 OCCPB5 / OCCP5 OCS0 OCS1 OCS2 OCS3 OCS4 OCS5 TMCSRL0 TMCSRH0 TMR0 / TMRD0 TMCSRL1 TMCSRH1 TMR1 / TMRD1 OPCLR OPCUR IPCLR IPCUR TCSR NCCR
Register
Output compare buffer register / Output compare register 0 Output compare buffer register / Output compare register 1 Output compare buffer register / Output compare register 2 Output compare buffer register / Output compare register 3 Output compare buffer register / Output compare register 4 Output compare buffer register / Output compare register 5 Compare control register 0 Compare control register 1 Compare control register 2 Compare control register 3 Compare control register 4 Compare control register 5 Timer control status register CH0 (lower) Timer control status register CH0 (upper) 16 bit timer register CH0 / 16-bit reload register CH0 Timer control status register CH1 (lower) Timer control status register CH1 (upper) 16 bit timer register CH1 / 16-bit reload register CH1 Output control lower register Output control upper register Input control lower register Input control upper register Timer control status register Noise cancellation control register
Byte Word access access
R/W
Resource name
Initial value
XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
-
R/W
-
R/W
-
R/W Output compare (CH0 ~ CH5)
-
R/W
XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 00000000B -0000000B 00000000B -0000000B 00000000B -0000000B 00000000B
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Waveform sequencer* 16-bit reload timer (CH1) 16-bit reload timer (CH0)
----0000B XXXXXXXXB XXXXXXXXB 00000000B ----0000B XXXXXXXXB XXXXXXXXB 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B
Prohibited area Program address detect control status register Delayed interrupt cause / clear register Low-power consumption mode register Clock selection register R/W R/W R/W R/W Prohibited area R/W R/W R/W R/W Watchdog timer Timebase timer X-XXX111B 1--00100B R/W R/W R/W R/W Address match detection Delayed interrupt Low-power consumption control register 00000000B -------0B 00011000B 11111100B
24
MB90460/5 Series
MB90460/5 series I/O map
Address
0000AAH ~ ADH 0000AEH 0000AFH 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH 0000C0H ~ FFH 001FF0H 001FF1H 001FF2H 001FF3H 001FF4H 001FF5H PADRL0 PADRM0 PADRH0 PADRL1 PADRM1 PADRH1 Program address detection register 0 (lower byte) Program address detection register 0 (middle byte) Program address detection register 0 (higher byte) Program address detection register 1 (lower byte) Program address detection register 1 (middle byte) Program address detection register 1 (higher byte) ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 Interrupt control register 07 Interrupt control register 08 Interrupt control register 09 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15 FMCS Flash memory control status register
Abbreviation
Register
Byte Word access access
Prohibited area R/W Prohibited area R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W External area R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Resource name
Initial value
Flash memory interface circuit
00010000B
00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B Interrupt controller 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B
XXXXXXXXB XXXXXXXXB XXXXXXXXB Address match detection XXXXXXXXB XXXXXXXXB XXXXXXXXB
R/W R/W R/W
25
MB90460/5 Series
MB90460/5 series I/O map
Address
003FE0H 003FE1H 003FE2H 003FE3H 003FE4H 003FE5H 003FE6H 003FE7H 003F78H 003FE9H 003FEAH 003FEBH 003FECH 003FEDH 003FEEH 003FEFH 003FF0H 003FF1H 003FF2H 003FF3H 003FF4H 003FF5H 003FF6H 003FF7H 003FF8H 003FF9H 003FFAH 003FFBH 003FFCH 003FFDH 003FFEH ~ 003FFFH
Abbreviation
OPDBR0
Register
Output data buffer register 0
Byte Word access access
R/W
Resource name
Initial value
00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B
OPDBR1
Output data buffer register 1
-
R/W
OPDBR2
Output data buffer register 2
-
R/W
OPDBR3
Output data buffer register 3
-
R/W
OPDBR4
Output data buffer register 4
-
R/W
OPDBR5
Output data buffer register 5
-
R/W
OPEBR6
Output data buffer register 6
-
R/W
OPEBR7
Output data buffer register 7
-
R/W
Waveform sequencer*
00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B XXXXXXXXB 0000XXXXB XXXXXXXXB XXXXXXXXB 00000000B 00000000B
OPEBR8
Output data buffer register 8
-
R/W
OPEBR9
Output data buffer register 9
-
R/W
OPEBRA
Output data buffer register A
-
R/W
OPEBRB
Output data buffer register B
-
R/W
OPDR
Output data register
-
R
CPCR
Compare clear register
-
R/W
TMBR
Timer buffer register
-
R
Prohibited area
26
MB90460/5 Series
* Meaning of abbreviations used for reading and writing R/W : Read and write enabled R : Read-only W : Write-only * Explanation of initial values 0 : The bit is initialized to 0. 1 : The bit is initialized to 1. X : The initial value of the bit is undefined. : The bit is not used. Its initial value is undefined. * Instruction using IO addressing e.g. MOV A, io, is not supported for registers area 003FE0H to 003FFFH. Note: For bits that is initialized by an reset operation, the initial value set by the reset operation is listed as an initial value. Note that the values are different from reading results. For LPMCR/CKSCR/WDTC, there are cases where initialization is performed or not performed, depending on the types of the reset. However initial value for resets that initializes the value are listed. *: These registers are not present in MB90465 series
27
MB90460/5 Series
INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
EI2OS support
X X X O O O O O O O O O O #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 #39 #40 #41 #42
Interrupt vector Number Address
FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH FFFF68H FFFF64H FFFF60H FFFF5CH FFFF58H FFFF54H
Interrupt cause
Reset INT9 instruction Exception processing A/D converter conversion termination Output compare channel 0 match End of measurement by PWC timer 0 / PWC timer 0 overflow* 16-bit PPG timer 0 Output compare channel 1 match 16-bit PPG timer 1* Output compare channel 2 match 16-bit reload timer 1 underflow Output compare channel 3 match DTP/ext. interrupt channels 0/1 detection DTTI0 Output compare channel 4 match DTP/ext. interrupt channels 2/3 detection DTTI1* Output compare channel 5 match End of measurement by PWC timer 1 / PWC timer 1 overflow DTP/ext. interrupt channels 4/5 detection Waveform sequencer timer compare match / write timing* DTP/ext. interrupt channels 6/7 detection Waveform sequencer position detect / compare interrupt* Waveform generator 16-bit timer 0/1/2 underflow 16-bit reload timer 0 underflow 16-bit free-running timer zero detect 16-bit PPG timer 2 Input capture channels 0/1 16-bit free-running timer compare clear Input capture channels 2/3 Timebase timer UART1 receive UART1 send UART0 receive UART0 send Flash memory status Delayed interrupt generator module
2
Interrupt control register ICR
ICR00
Priority *2
High
Address
0000B0H*1
08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH
ICR01
0000B1H*1
ICR02 ICR03
0000B2H*1 0000B3H*1
ICR04
0000B4H*1
O O
ICR05
0000B5H*2
O O O O O O
ICR06
0000B6H*1
ICR07
0000B7H*1
ICR08
0000B8H*1
O
ICR09
0000B9H*1
O O
ICR10 ICR11 ICR12 ICR13 ICR14 ICR15
0000BAH*1 0000BBH*1 0000BCH*1 0000BDH*1 0000BEH*1 0000BFH*1
O

Low
: Can be used and support the EI OS stop request. O : Can be used and interrupt request flag is cleared by EI2OS interrupt clear signal. X : Cannot be used. : Usable when an interrupt cause that shares the ICR is not used. * : In MB90465 series, these resources are not present, therefore, interrupt not available.
28
MB90460/5 Series
PERIPHERAL RESOURCES
1. Low-power Consumption Control Circuit
The MB90460 series has the following CPU operating mode configured by selection of an operating clock and clock operation control. * Clock mode PLL clock mode : A PLL clock that is a multiple of the oscillation clock (HCLK) frequency is used to operate the CPU and peripheral functions. Main clock mode : The main clock, with a frequency one-half that of the oscillation clock (HCLK), is used to operate the CPU and peripheral functions. In main clock mode, the PLL multiplier circuit is inactive. * CPU intermittent operation mode CPU intermittent operation mode causes the CPU to operate intermittently, while high-speed clock pulses are supplied to peripheral functions, reducing power consumption. In CPU intermittent operation mode, intermittent clock pulses are only applied to the CPU when it is accessing a register, internal memory, a peripheral function, or an external unit. * Standby mode In standby mode, the low power consumption control circuit stops supplying the clock to the CPU (sleep mode) or the CPU and peripheral functions (timebase timer mode), or stops the oscillation clock itself (stop mode), reducing power consumption. * PLL sleep mode PLL sleep mode is activated to stop the CPU operating clock when the microcontroller enters PLL clock mode; other components continue to operate on the PLL clock. * Main sleep mode Main sleep mode is activated to stop the CPU operating clock when the microcontroller enters main clock mode; other components continue to operate on the main clock. * PLL timebase timer mode PLL timebase timer mode causes microcontroller operation, with the exception of the oscillation clock, PLL clock and timebase timer, to stop. All functions other than the timebase timer are deactivated. * Main timebase timer mode Main timebase timer mode causes microcontroller operation, with the exception of the oscillation clock, main clock and the timebase timer, to stop. All functions other than the timebase timer are deactivated. * Stop mode Stop mode causes the source oscillation to stop. All functions are deactivated. (1) Register configuration
Clock Selection Register Address: 00000A1H Read/write Initial value
15
14 MCM R 1
13 WS1 R/W 1
12 WS0 R/W 1
11
Reserved
10 MCS R/W 1
9 CS1 R/W 0
8 CS0 R/W 0
Bit number CKSCR
Reserved
R/W 1
R/W 1
Low-power Consumption Mode Control Register 7 Address: 0000A0H Read/write Initial value STP W 0 6 SLP W 0 5 SPL R/W 0 4 RST W 1 3 TMDX W 1 2 CG1 R/W 0 1 CG0 R/W 0 0
Reserved
Bit number LPMCR
R/W 0
29
MB90460/5 Series
(2) Block diagram
Low power mode control register (LPMCR) STP SLP SPL RST TMD CG1 CG0 RESV Pin high impedance control circuit Internal reset generation circuit
CPU intermittent operation selecter
Pin Hi-z control
RSTX Pin
Internal reset
Select intermittent cycles CPU clock control circuit CPU clock
Release reset
3
RST Standby control circuit Stop and sleep signals
Cancel interrupt Stop signal
Clock generator Clock selector
Machine clock Peripheral clock Oscillation stabiliz- control circuit -ation wait is passed
Peripheral clock
2 2
x1 x2 x3 x4
Oscillation stabilization wait interval selector
PLL multipiler circuit
RESV MCM WS1 WS0 RESV MCS CS1 Clock selection register (CKSCR)
CS0
X0
Pin System clock generation circuit
Divideby-2
Divideby-512
Divideby-2
Divideby-4
Divideby-4
Divideby-4
Main clock X1 Pin
Timebase timer
30
MB90460/5 Series
2. I/O Ports
(1) Outline of I/O ports When a data register serving for control output is read, the data output from it as a control output is read regardless of the value in the direction register. Note that, if a read-modify-write instruction (such as a bit set instruction) is used to preset output data in the data register when changing its setting from input to output, the data read is not the data register latched value but the input data from the pin. Also note that, for port (other than Port 0, 1, 2 and 3) that is multiplexed with resource, use read-modify-write instruction may accidentally write unexpected value to the DDR and PDR register when resource is enabled. Ports 0 to 4 and Port 6 are input/output ports which serve as inputs when the direction register value is "0" or as outputs when the value is "1". Port 5 are input/output ports as other port when ADER is 00H. (2) Register configuration
Port 0 Data Register Address: 000000H Read/write Initial value Port 1 Data Register Address: 000001H Read/write Initial value Port 2 Data Register Address: 000002H Read/write Initial value Port 3 Data Register Address: 000003H Read/write Initial value Port 4 Data Register Address: 000004H Read/write Initial value Port 5 Data Register Address: 000005H Read/write Initial value Port 6 Data Register Address: 000006H Read/write Initial value 15 P57 R/W X 7 7 P07 R/W X 15 P17 R/W X 7 P27 R/W X 15 P37 R/W X 7 6 P06 R/W X 14 P16 R/W X 6 P26 R/W X 14 P36 R/W X 6 P46 R/W X 14 P56 R/W X 6 5 P05 R/W X 13 P15 R/W X 5 P25 R/W X 13 P35 R/W X 5 P45 R/W X 13 P55 R/W X 5 4 P04 R/W X 12 P14 R/W X 4 P24 R/W X 12 P34 R/W X 4 P44 R/W X 12 P54 R/W X 4 3 P03 R/W X 11 P13 R/W X 3 P23 R/W X 11 P33 R/W X 3 P43 R/W X 11 P53 R/W X 3 P63 R/W X 2 P02 R/W X 10 P12 R/W X 2 P22 R/W X 10 P32 R/W X 2 P42 R/W X 10 P52 R/W X 2 P62 R/W X 1 P01 R/W X 9 P11 0 P00 R/W X 8 P10 R/W X 0 P20 R/W X 8 P30 R/W X 0 P40 R/W X 8 P50 R/W X 0 P60 R/W X Bit number PDR6 Bit number PDR5 Bit number PDR4 Bit number PDR3 Bit number PDR2 Bit number PDR1 Bit number PDR0
R/W
X 1 P21 R/W X 9 P31 R/W X 1 P41 R/W X 9 P51 R/W X 1 P61 R/W X
(Continued) 31
MB90460/5 Series
(Continued)
Port 0 Direction Register Address: 000010H Read/write Initial value Port 1 Direction Register Address: 000011H Read/write Initial value Port 2 Direction Register Address: 000012H Read/write Initial value Port 3 Direction Register Address: 000013H Read/write Initial value Port 4 Direction Register Address: 000014H Read/write Initial value Port 5 Direction Register Address: 000015H Read/write Initial value Port 6 Direction Register Address: 000016H Read/write Initial value Port 5 Analog Input Enable Register 15 14 Address: 000017H Read/write Initial value ADE7 R/W 1 ADE6 R/W 1 15 D57 R/W 0 7 7 D07 R/W 0 15 D17 R/W 0 7 D27 R/W 0 15 D37 R/W 0 7 6 D06 R/W 0 14 D16 R/W 0 6 D26 R/W 0 14 D36 R/W 0 6 D46 R/W X 14 D56 R/W 0 6 5 D05 R/W 0 13 D15 R/W 0 5 D25 R/W 0 13 D35 R/W 0 5 D45 R/W X 13 D55 R/W 0 5 4 D04 R/W 0 12 D14 R/W 0 4 D24 R/W 0 12 D34 R/W 0 4 D44 R/W X 12 D54 R/W 0 4 3 D03 R/W 0 11 D13 R/W 0 3 D23 R/W 0 11 D33 R/W 0 3 D43 R/W X 11 D53 R/W 0 3 D63 R/W 0 13 ADE5 R/W 1 12 ADE4 R/W 1 11 ADE3 R/W 1 2 D02 R/W 0 10 D12 R/W 0 2 D22 R/W 0 10 D32 R/W 0 2 D42 R/W X 10 D52 R/W 0 2 D62 R/W 0 10 ADE2 R/W 1 1 D01 R/W 0 9 D11 R/W 0 1 D21 R/W 0 9 D31 R/W 0 1 D41 R/W X 9 D51 R/W 0 1 D61 R/W 0 9 ADE1 R/W 1 0 D00 R/W 0 8 D10 R/W 0 0 D20 R/W 0 8 D30 R/W 0 0 D40 R/W X 8 D50 R/W 0 0 D60 R/W 0 8 ADE0 R/W 1 Bit number ADER Bit number DDR6 Bit number DDR5 Bit number DDR4 Bit number DDR3 Bit number DDR2 Bit number DDR1 Bit number DDR0
(Continued)
32
MB90460/5 Series
(Continued)
Port 0 Pull-up Resistor Setting Register 7 6 Address: 00001CH Read/write Initial value RD07 R/W 0 RD06 R/W 0
5 RD05 R/W 0 13 RD15 R/W 0
4 RD04 R/W 0 12 RD14 R/W 0
3 RD03 R/W 0 11 RD13 R/W 0
2 RD02 R/W 0 10 RD12 R/W 0
1 RD01 R/W 0 9 RD11 R/W 0
0 RD00 R/W 0 8 RD10 R/W 0
Bit number RDR0
Port 1 Pull-up Resistor Setting Register 15 14 Address: 00001DH Read/write Initial value RD17 R/W 0 RD16 R/W 0
Bit number RDR1
(3) Block diagram * Block diagram of Port 0 pins
RDR Resource output Port data register (PDR) Direct resource input Resource output enable
Pull-up resistor About 50K
Internal data bus
PDR read
Output latch
PDR write Pin Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
(Continued)
33
MB90460/5 Series
(Continued) * Block diagram of Port 1 pins
RDR Resource output Port data register (PDR) Resource input Resource output enable
Pull-up resistor About 50K
PDR read
Internal data bus
Output latch
PDR write Pin Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
* Block diagram of Port 2 pins
Resource output Port data register (PDR)
Resource input Resource output enable
Internal data bus
PDR read
Output latch
PDR write Pin Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
(Continued)
34
MB90460/5 Series
(Continued) * Block diagram of Port 3 pins
Resource output Resource output enable Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write Pin Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
* Block diagram of Port 4 pins
Resource output Port data register (PDR)
Resource input Resource output enable
PDR read
Internal data bus
Output latch
PDR write Pin Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
(Continued)
35
MB90460/5 Series
(Continued) * Block diagram of Port 5 pins
ADER Port data register (PDR) Analog input
Internal data bus
PDR read
Output latch
PDR write Port data direction register (DDR)
Direction latch
Pin
DDR write
DDR read
Standby control (SPL = 1)
* Block diagram of Port 6 pins
Resource output Port data register (PDR)
Resource input Resource output enable
Internal data bus
PDR read
Output latch
PDR write Pin Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
External interrupt enable
36
MB90460/5 Series
3. Timebase Timer
The timebase timer is an 18-bit free-running counter (timebase counter) that counts up in synchronization with the internal count clock (one-half of the source oscillation). Features of timebase timer : * Interrupt generated when counter overflow * EI2OS supported * Interval timer function: An interrupt generated at four different time intervals * Clock supply function: Four different clock can be selected as watchdog timer's count clock Supply clock for oscillation stabilization (1) Register configuration
Timebase Timer Control Register 15 Address: 0000A9H Read/write Initial value
Reserved
14
13
12 TBIE R/W 0
11 TBOF R/W 0
10 TBR W 1
9 TBC1 R/W 0
8 TBC0 R/W 0
Bit number TBTC
R/W 1
(2) Block diagram
To watchdog timer Timebase timer counter Divide-by -two HCLK x21 x22 x23 ... ... x28 x29 x210 x211 x212 x213 x214 x215 x216 x217 x218
OF Counter clear
OF
OF
OF To the oscillation setting time selector in the clock control section
Power-on reset Stop mode start CKSCR: MCS = 1 to 0(*1)
Counter clear circuit TBOF clear
Interval timer selector TBOF set
Timebase timer interrupt signal #36 (24H)(*2) -- -- -- TBIE TBOF Timebase timer TBR TBC1 TBC0 interrupt register (TBTC)
OF: Overflow HCLK: Oscillation clock *1 Switching of the machine clock from the oscillation clock to the PLL clock *2 Interrupt number
37
MB90460/5 Series
4. Watchdog Timer
The watchdog timer is a 2-bit counter that uses the timebase timer's supply clock as the count clock. After activation, if the watchdog timer is not cleared within a given period, the CPU will be reset. * Features of watchdog timer : Reset CPU at four different time intervals Status bits to indicate the reset causes (1) Register configuration
Watchdog Timer Control Register 7 Address: 0000A8H Read/write Initial value PONR R X 6 5 WRST R X 4 ERST R X 3 SRST R X 2 WTE W 1 1 WT1 W 1 0 WT0 W 1 Bit number WDTC
(2) Block diagram
Watchdog timer control register (WDTC)
Watchdog timer Activation with CLR Start of sleep mode Start of hold status mode Start of stop mode
Counter clear control circuit Count clock selector
2-bit counter
OverWatchdog flow reset generator
To the internal reset generator
Clear
(Timebase timer counter) One-half of HCLK
HCLK: Oscillation clock
38
MB90460/5 Series
5. 16-bit reload timer (x 2)
The 16-bit reload timer provides two operating mode, internal clock mode and event count mode. In each operating mode, the 16-bit down counter can be reloaded (reload mode) or stopped when underflow (one-shot mode). Output pins TO1 ~ TO0 are able to output different waveform accroding to the counter operating mode. TO1 ~ TO0 toggles when counter underflow if counter is operated as reload mode. TO1 ~ TO0 output specified level (H or L) when counter is counting if the counter is in one-shot mode. Features of the 16 bit reload timer : * Interrupt generated when timer underflow * EI2OS supported * Internal clock operating mode : Three internal count clocks can be selected Counter can be activated by software or exteranl trigger (signal at TIN1 ~ TIN0 pin) Counter can be reloaded or stopped when underflow after activated * Event count operating mode : Counter counts down by one when specified edge at TIN1 ~ TIN0 pin Counter can be reloaded or stopped when underflow (1) Register configuration
16-bit Timer Register (Upper) Address: ch0 000085H ch1 000089H Read/write Initial value
15 D14 R/W X 7 D07 R/W X
14 D13 R/W X 6
13 D12 R/W X 5
12 D11 R/W X 4
11 D10 R/W X 3
10 D09 R/W X 2
9 D08 R/W X 1
8
Bit number TMR0 ~ 1 / TMRD0 ~ 1
D15 R/W X
16-bit Timer Register (Lower) Address: ch0 000084H ch1 000088H Read/write Initial value
0
Bit number TMR0 ~ 1 / TMRD0 ~ 1
D06 R/W X
D05 R/W X
D04 R/W X
D03 R/W X
D02 R/W X
D01 R/W X
D00 R/W X
Timer Control Status Register (Upper) 15 Address: ch0 000083H ch1 000087H Read/write Initial value Timer Control Status Register (Lower) Address: ch0 000082H ch1 000086H Read/write Initial value
14
13
12 CSL1 R/W 0
11
10
9
8
Bit number TMCSRH0 ~ 1
CSL0 MOD2 MOD1 R/W 0 3 UF R/W 0 R/W 0 2 CNTE R/W 0 R/W 0 1 TRG R/W 0 0
7
6
5
4 INTE R/W 0
Bit number TMCSRL0 ~ 1
MOD0 OUTE OUTL RELD R/W 0 R/W 0 R/W 0 R/W 0
Note : Registers TMR0~1/TMRD0~1 are word access only. 39
MB90460/5 Series
(2) Block diagram
F2MC-16LX bus
TMRD0*1
16-bit reload register
Reload signal Reload control circuit
16-bit timer register Count clock generation circuit Machine clock Prescaler Clear Internal clock Pin
P15 P20
Gate input
Valid clock judgment circuit
Wait signal To UART0 and UART1 (*1) Pin P16/TO0(*1)
Operation control circuit
Output control circuit Clock selector
Output signal generation Invert circuit
Input control circuit
External clock Select signal Function selection
Timer control status register (TMCSR0)(*1)
Interrupt request signal #30 (1EH)(*2) <#18 (12H)>
*1 This register includes channel 0 and channel 1. The register enclosed in < and > indicates the
channel 1 register.
*2 Interrupt number
40
MB90460/5 Series
6. 16-bit PPG Timer ( x 3, PPG1 is not present in MB90465 series)
The 16-bit PPG timer consists of a 16-bit down counter, prescaler, 16-bit period setting register, 16-bit duty setting register, 16-bit control register and a PPG output pin. This module can be used to output pulses synchronized by software trigger or GATE signal from Multi-functional timer, refer to "Multi-functional Timer". Features of 16-bit PPG timer : * Two operating mode : PWM and One-shot * 8 types of counter operation clock (, /2, /4, /8, /16, /32, /64, /128) can be selected * Interrupt is generated when trigger signal arrived, or counter borrow, or change of PPG output * EI2OS supported (1) Register configuration
PPG Control Status Register (Upper) Address: ch0 00003FH ch1 000047H ch2 00004FH Read/write Initial value 15 14 13 12 11 10 9 8 Bit number PCNTH0 ~ 2 CNTE STGR MDSE RTRG CKS2 R/W 0 7 Address: ch0 00003EH ch1 000046H ch2 00004EH Read/write Initial value R/W 0 6 IREN R/W 0 R/W 0 5 IRQF R/W 0 R/W 0 4 IRS1 R/W 0 R/W 0 3 IRS0 R/W 0 CKS1 CKS0 PGMS R/W 0 2 R/W 0 1 R/W 0 0 Bit number PCNTL0 ~ 2
PPG Control Status Register (Lower)
POEN OSEL R/W 0 R/W 0
PPG Duty Setting Register (Upper) 15 14 13 12 11 10 9 8 Address: ch0 00003DH ch1 000045H DU15 DU14 DU13 DU12 DU11 DU10 DU09 DU08 ch2 00004DH Read/write Initial value W X W X 7 DU06 W X W X 6 DU05 W X W X 5 DU04 W X W X 4 W X 3 W X 2 DU01 W X W X 1 DU00 W X 0
Bit number PDUT0 ~ 2
PPG Duty Setting Register (Lower) Address: ch0 00003CH ch1 000044H ch2 00004CH Read/write Initial value
Bit number PDUT0 ~ 2
DU07 W X
DU03 DU02 W X W X
PPG Period Setting Register (Upper) 15 14 13 12 11 10 9 8 Address: ch0 00003BH ch1 000043H CS15 CS14 CS13 CS12 CS11 CS10 CS09 CS08 ch2 00004BH Read/write Initial value Address: ch0 00003AH ch1 000042H ch2 00004AH Read/write Initial value W X W X 7 W X 6 W X 5 W X 4 W X 3 CS02 W X W X 2 CS01 W X W X 1 CS00 W X 0
Bit number PCSR0 ~ 2
PPG Period Setting Register (Lower)
Bit number PCSR0 ~ 2
CS07 W X
CS06 CS05 W X W X
CS04 CS03 W X W X
(Continued) 41
MB90460/5 Series
(Continued)
PPG Down Counter Register (Upper) 15 14 13 12 11 10 Address: ch0 000039H ch1 000041H DC15 DC14 DC13 DC12 DC11 DC10 DC09 ch2 000049H Read/write Initial value R 1 R 1 7 Address: ch0 000038H ch1 000040H ch2 000048H Read/write Initial value DC07 DC06 R 1 R 1 R 1 6 DC05 R 1 R 1 5 DC04 R 1 R 1 4 DC03 R 1 R 1 3 DC02 R 1 R 1 2 DC01 R 1 9 DC08 R 1 1 DC00 R 1 0 Bit number PDCR0 ~ 2 8 Bit number PDCR0 ~ 2
PPG Down Counter Register (Lower)
Note : Registers PDCR0~2, PDSR0~2 and PDUT0~2 are word access only (2) Block diagram
Period Setting Buffer Register 0/1/2
Period Setting Buffer Register 0/1/2
Prescaler
CKS2 CKS1 CKS0
Period Setting Register 0/1/2
Duty Setting Register 0/1/2
1/1 1/2 1/4 1/8 1/16 1/32 1/64 1/128
Comparator CLK LOAD
P37/PPG0 or P36/PPG1 or P46/PPG2
Pin
16-bit down counter
MDSE PGMS OSEL POEN
STOP START BORROW
Machine clock
F2MC-16LX bus
S
Down Counter Register 0/1/2
Q
PPG0 (multi-functional timer) or PPG1 (multi-pulse generator) or PPG2
R
Interrupt selection
GATE - from multi-functional timer (for PPG ch. 0 only)
Interrupt
#14, #16, #32
Edge detection
IRS1
IRS0
IRQF
IREN
(for PPG ch. 1 & 2) STGR CNTE RTRG
42
MB90460/5 Series
7. Multi-functional Timer
The 16-bit multi-functional timer module consists of one 16-bit free-running timer, four input capture circuits, six output comparators and one channel of 16-bit PPG timer. This module allows six independent waveforms generated by PPG timer or waveform generator to be outputted. With the 16-bit free-running timer and the input capture circuit, input pulse width and external clock period measurement can be done. (1) 16-bit free-running timer (1 channel) * The 16-bit free-running timer consists of a 16-bit up/up-down counter, control register, 16-bit compare clear register (with buffer register) and a prescaler. * 8 types of counter operation clock (, /2, /4, /8, /16, /32, /64, /128) can be selected. ( is the machine clock) * Two types of interrupt causes : - Compare clear interrupt is generated when there is a comparing match with compare clear register and 16bit free-running timer. - Zero detection interrupt is generated while 16-bit free-running timer is detected as zero in count value. * EI2OS supported. * Compare-clear register buffer provided : The selectable buffer enables the 16-bit free-running timer update its compare-clear register automatically without stop the timer operation. User can read the next compare-clear value to the compare-clear reigster when the timer is running. The compare-clear register will be updated when the timer value is "0000H" * Reset, software clear, compare match with compare clear register in up-count mode will reset the counter value to "0000H". * Supply clock to output compare module : The prescaler ouptut is acted as the count clock of the output compare. (2) Output compare module ( 6 channels) * The output compare module consists of six 16-bit compare registers (with selectable buffer register), compare output latch and compare control registers. An interrupt is generated and output level is inverted when the value of 16-bit free-running timer and compare register are matched. * 6 compare registers can be operated independently. * Output pins and interrupt flag are corresponding to each compare register. * 2 compare registers can be paired to control the output pins. * Inverts output pins by using 2 compare registers together. * Setting the initial value for each output pin is possible. * Interrupt generated when there is a comparing match with output compare register and 16-bit free-running timer. * EI2OS supported. (3) Input capture module (4 channels) Input capture consists of 4 independent external input pins, the corresponding capture register and capture control register. By detecting any edge of the input signal from the external pin, the value of the 16-bit freerunning timer can be stored in the capture register and an interrupt is generated simultaneously. * Operations synchronized with the 16-bit free-running timer's count clock. * 3 types of trigger edge (rising edge, falling edge and both edge) of the external input signal can be selected and there is indication bit to show the trigger edge is rising or falling. * 4 input captures can be operated independently. * Two independent interrupts are generated when detecting a valid edge from external input. * EI2OS supported. (Continued) 43
MB90460/5 Series
(Continued) (4) 16-bit PPG timer (x 1) The 16-bit PPG timer 0 is used to provide a PPG signal for waveform generator. (See section " PERIPHERAL RESOURCES", "6. 16-bit PPG Timer") (5) Waveform generator module The waveform generator consists of three 16-bit timer registers, three timer control registers and 16-bit waveform control register. With waveform generator, it is possible to generate real time output, 16-bit PPG waveform output, non-overlap 3-phase waveform output for inverter control and DC chopper waveform output. * It is possible to generate a non-overlap waveform output based on dead-time of 16-bit timer. (Dead-time timer function) * It is possible to generate a non-overlap waveform output when realtime output is operated in 2-channel mode. (Dead-time timer function) * By detecting realtime output compare match, GATE signal of the PPG timer operation will be generated to start or stop PPG timer operation. (GATE function) * When a match is detected by real time output compare, the 16-bit timer is activated. The PPG timer can be started or stopped easily by generating a GATE signal for PPG operation until the 16-bit timer stops. (GATE function) * Force to stop output waveform using DTTI0 pin input. * Interrupt is generated when DTTI0 active or 16-bit tmer underflow. * EI2OS supported. (6) Register configuration * 16-bit free-running timer registers
Timer Control Status Register (Upper) 15 14 Address: 00005FH Read/write Initial value 13 12 MSI2 R/W 0 4 11 MSI1 R/W 0 3 SCLR R/W 0 11 T11 R/W 0 3 T03 R/W 0 10 MSI0 R/W 0 2 CLK2 R/W 0 10 T10 R/W 0 2 T02 R/W 0 9 ICLR R/W 0 1 CLK1 R/W 0 9 T09 R/W 0 1 T01 R/W 0 8 ICRE R/W 0 0 CLK0 R/W 0 8 T08 R/W 0 0 T00 R/W 0 Bit number TCDT Bit number TCDT Bit number TCCSL Bit number TCCSH
ECKE IRQZF IRQZE R/W 0 R/W 0 R/W 0 5
Timer Control Status Register (Lower) 7 6 Address: 00005EH Read/write Initial value Timer Data Register (Upper) Address: 00005DH Read/write Initial value Timer Data Register (Lower) Address: 00005CH Read/write Initial value 15 T15 R/W 0 7 T07 R/W 0 BFE R/W 0 14 T14 R/W 0 6 T06 R/W 0
STOP MODE R/W 1 13 T13 R/W 0 5 T05 R/W 0 R/W 0 12 T12 R/W 0 4 T04 R/W 0
(Continued) 44
MB90460/5 Series
(Continued)
Compare Clear Buffer Register / Compare Clear Register (Upper) 15 14 13 12 11 Address: 00005BH Read/write Initial value CL15 R/W 1 CL14 R/W 1 CL13 R/W 1 CL12 R/W 1 CL11 R/W 1 10 CL10 R/W 1 9 CL09 R/W 1 8 CL08 R/W 1 Bit number CPCLRB/CPCLR
Compare Clear Buffer Register / Compare Clear Register (Lower) 7 6 5 4 3 Address: 00005AH Read/write Initial value CL07 R/W 1 CL06 R/W 1 CL05 R/W 1 CL04 R/W 1 CL03 R/W 1
2 CL02 R/W 1
1 CL01 R/W 1
0 CL00 R/W 1
Bit number CPCLRB/CPCLR
Note : Registers TCDT, CPCLRB/CPCLR are word access only. * Output compare registers
Compare Control Register (Upper) 15 Address: ch1 00007DH ch3 00007FH ch5 000081H Read/write Initial value Compare Control Register (Lower) 7 Address: ch0 00007CH ch2 00007EH ch4 000080H Read/write Initial value IOP1 R/W 0 IOP0 R/W 0 6 IOE1 R/W 0 5 IOE0 R/W 0 4 BUF1 R/W 1 3 BUF0 R/W 1 2 1 0 Bit number OCS0/2/4 CST1 CST0 R/W 0 R/W 0 BTS1 R/W 1 14 13 12 11 10 9 8 Bit number OCS1/3/5 BTS0 CMOD OTE1 OTE0 OTD1 OTD0 R/W 1 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
Output Compare Buffer Register / Output Compare Register (Upper) Address: ch0 000071H ch1 000073H ch2 000075H 15 14 13 12 11 10 9 8 ch3 000077H ch4 000079H ch5 00007BH OP15 OP14 OP13 OP12 OP11 OP10 OP09 OP08 Read/write Initial value R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X
Bit number OCCPB0 ~ 5/ OCCP0 ~ 5
Output Compare Buffer Register / Output Compare Register (Lower) Address: ch0 000070H ch1 000072H ch2 000074H ch3 000076H ch4 000078H ch5 00007AH Read/write Initial value
7 OP07 R/W X OP06 R/W X
6 OP05 R/W X
5 OP04 R/W X
4 OP03 R/W X
3
2
1 OP00 R/W X
0
Bit number OCCPB0 ~ 5/ OCCP0 ~ 5
OP02 OP01 R/W X R/W X
Note : Register OCCPB0~5/OCCP0~5 are word access only. 45
MB90460/5 Series
* Input capture registers
Input Capture Control Status Register (2/3) (Upper) 15 Address: 00006BH Read/write Initial value Input Capture Control Status Register (2/3) (Lower) 7 Address: 00006AH Read/write Initial value ICP3 R/W 0 6 ICP2 R/W 0 5 ICE3 R/W 0 4 ICE2 R/W 0 3 EG31 R/W 0 2 EG30 R/W 0 1 EG21 R/W 0 0 EG20 R/W 0 Bit number ICSL23 14 13 12 11 10 9 IEI3 R 0 8 IEI2 R 0 Bit number ICSH23
PPG output control/ Input Capture Control Status Register (0/1) (Upper) 15 14 13 12 11 10 Address: 000069H Read/write Initial value PGEN5 PGEN4 PGEN3 PGEN2 PGEN1 PGEN0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
9 IEI1 R 0
8 IEI0 R 0
Bit number PICSH01
Input Capture Control Register (0/1) 7 Address: 000068H Read/write Initial value ICP1 R/W 0 6 ICP0 R/W 0 5 ICE1 R/W 0 4 ICE0 R/W 0 3 EG11 R/W 0 2 EG10 R/W 0 1 EG01 R/W 0 0 EG00 R/W 0 Bit number PICSL01
Input Capture Data Register (Upper) Address: ch0 000061H ch1 000063H ch2 000065H ch3 000067H Read/write Initial value 15 CP15 R X CP14 R X 14 CP13 R X 13 CP12 R X 12 CP11 R X 11 CP10 R X 10 CP09 R X 9 CP08 R X 8 Bit number IPCP0 ~ 3
Input Capture Data Register (Lower) Address: ch0 000060H ch1 000062H ch2 000064H ch3 000066H Read/write Initial value 7 CP07 R X CP06 R X 6 CP05 R X 5 CP04 R X 4 CP03 R X 3 CP02 R X 2 CP01 R X 1 CP00 R X 0 Bit number IPCP0 ~ 3
Note : Registers IPCP0~3 are word access only.
46
MB90460/5 Series
* Waveform generator registers
Waveform Control Register 15 Address: 000059H Read/write Initial value DTIE R/W 0 14 DTIF R/W 0 7 Address: ch0 000056H ch2 000058H Read/write Initial value 13 NRSL R/W 0 6 12 DCK2 R/W 0 5 11 DCK1 R/W 0 4 3 10 DCK0 R/W 0 2 9 8 Bit number SIGCR NWS1 NWS0 R/W 0 1 R/W 0 0
16-bit Timer Control Register Bit number DTCR0, DTCR2 DMOD GTEN1 GTEN0 TMIF R/W 0 R/W 0 R/W 0 R/W 0 TMIE TMD2 TMD1 TMD0 R/W 0 R/W 0 R/W 0 R/W 0
16-bit Timer Control Register 15 Address: ch1 000057H Read/write Initial value
14
13
12
11 TMIE R/W 0
10
9
8
Bit number DTCR1
DMOD GTEN1 GTEN0 TMIF R/W 0 R/W 0 R/W 0 R/W 0
TMD2 TMD1 TMD0 R/W 0 R/W 0 R/W 0
16-bit Timer Register (Upper) 15 Address: ch0 000051H ch1 000053H ch2 000055H Read/write Initial value 16-bit Timer Register (Lower) Address: ch0 000050H ch1 000052H ch2 000054H Read/write Initial value TR15 R/W X TR14 R/W X 7 TR07 R/W X TR06 R/W X 14 TR13 R/W X 6 TR05 R/W X 13 TR12 R/W X 5 TR04 R/W X 12 TR11 R/W X 4 TR03 R/W X 11 TR10 R/W X 3 TR02 R/W X 10 TR09 R/W X 2 TR01 R/W X 9 TR08 R/W X 1 TR00 R/W X 0 8
Bit number TMRR0~2
Bit number TMRR0~2
Note : Registers TMRR0 ~ 2 are word access only
47
MB90460/5 Series
(7) Block diagram * Block diagram of Multi-functional timer
Real time I/O
RTO0 Interrupt #12 Interrupt #15 Interrupt #17 Interrupt #19 Interrupt #21 Interrupt #23 Output compare 0 Output compare 1 Output compare 2 Output compare 3 Output compare 4 Output compare 5 Pin P30/RTO0 (U)
RTO1
Pin
P31/RTO1 (X)
16-bit output compare
RTO2
Pin
P32/RTO2 (V)
RTO3 RT0 ~ 5 RT0 ~5
Pin
P33/RTO3 (Y)
Waveform generator
Buffer transfer Counter value
RTO4
Pin
P34/RTO4 (W)
RTO5
Pin
P35/RTO5 (Z)
DTTI
Pin
P10/INT0/DTTI0
F2MC-16LX bus
Interrupt #31 Interrupt #34
Zero detect Compare clear
Interrupt #29
16-bit timer 0/1/2 underflow
DTTI0 falling edge detect
16-bit freerunning timer
Interrupt #20 A/D trigger A/D trigger PPG0 GATE
PPG0 GATE
EXCK
Pin
P17/FRCK
Counter value
Interrupt #33 Interrupt #35
Input capture 0/1 Input capture 2/3 P24/IN0
IN0
Pin
16-bit input capture
IN1
Pin
P25/IN1
IN2
Pin
P26/IN2
IN3
Pin
P27/IN3
(Continued)
48
MB90460/5 Series
(Continued) * Block diagram of 16-bit free-running timer
STOP MODE SCLR CLK2 CLK1 CLK0 Prescaler
STOP
UP/UP-DOWN
CLR
16-bit free-running timer
Zero detect circuit
CK
Zero detect (to output compare)
To input capture & output compare
Transfer
16-bit compare clear register F2MC-16LX bus
Compare circuit
Compare clear match (to output compare)
16-bit compare clear buffer register
I0 I1 O
Selector
Interrupt #31 (1FH)
Selector
Mask circuit
I0
I1 O
I0 I1 O
Interrupt #34 (22H)
Selector A/D trigger
MSI2
MSI1
MSI0
ICLR
ICRE
IRQZF
IRQZE
I0 I1 O
Selector
(Continued)
49
MB90460/5 Series
(Continued) * Block diagram of 16-bit output compare
Count value from free-running timer BUF0
Compare buffer register 0/2/4
I0 O I1
BTS0
Zero detect from free-running timer Compare clear match from free-running timer
Transfer
Compare register 0/2/4 F2MC-16LX bus
Selector
BUF1
Compare circuit
BTS1
I0 O
Compare buffer register 1/3/5
I1
Selector
Transfer
Compare register 1/3/5
CMOD
T
Q
RT0/2/4 (Waveform generator) RT1/3/5 (Waveform generator) Interrupt #12, #17, #21 #15, #19, #23
Compare circuit
T
IOP1 IOP0 IOE1 IOE0
Q
* Block diagram of 16-bit input capture
Count value from free-running timer
Capture register 0/2
Edge detect
IN0/2
F2MC-16LX bus
EG11
EG10 EG01
EG00
IEI1
IEI0
Capture register 1/3
Edge detect
IN1/3
ICP0
ICP1
ICE0
ICE1
Interrupt #33, #35 #33, #35
(Continued)
50
MB90460/5 Series
(Continued) * Block diagram of waveform generator
DCK2 DCK1 DCK0 NRSL DTIF DTIE NWS1 NWS0 DTTI0 control circuit
PICSH01 DTCR0 TMD2 TMD1 PGEN1 PGEN0 GATE 0/1 TMD0 GTEN1 GTEN0
SIGCR
Divider
Noise cancellation
DTTI0
TO0 RT0 RT1 Waveform control TO1 Output control
GATE (to PPG0)
Selector
16-bit timer 0 Compare circuit Selector
RTO0 (U)
U 16-bit timer register 0 DTCR1 TMD2 TMD1 TMD0 GTEN1 GTEN0 PGEN3 PGEN2 TO2 RT2 RT3 Waveform control TO3 Output control Dead time generator X GATE 2/3
RTO1 (X)
F2MC-16LX bus
PICSH01
Selector
16-bit timer 1 Compare circuit Selector
RTO2 (V)
V 16-bit timer register 1 DTCR2 TMD2 TMD1 TMD0 GTEN1 GTEN0 Dead time generator Y GATE 4/5
RTO3 (Y)
PICSH01 PGEN5 PGEN4 TO4 RT4 RT5 Waveform control TO5 Output control
Selector
16-bit timer 2 Compare circuit Selector
RTO4 (W)
W 16-bit timer register 2 Dead time generator Z
RTO5 (Z)
PPG0
51
MB90460/5 Series
8. Multi-pulse Generator (Not present in MB90465 series, but the 16-bit reload timer 0 can be used individually)
The Multi-pulse generator consists of a 16-bit PPG timer, a 16-bit reload timer and a waveform sequencer. The Multi-pulse generator has the following features : * Output signal control - 12 output data buffer registers are provided - Output data register can be updated by any one of output data buffer registers when : 1. an effective edge detected at SNI2 ~ SNI0 pin 2. 16-bit reload timer underflow 3. output data buffer register OPDBR0 is written * Output data register (OPDR) determines which OPT terminals (OPT5 ~ 0) output the 16-bit PPG waveform - Waveform sequencer is provided with a 16-bit timer to measure the speed of motor - The 16-bit timer can be used to disable the OPT output when the position detection is missing * Input position detect control - SNI2 ~ SNI0 input can be used to detect the rotor position - A controllable noise filter is provided to the SNI2 ~ SNI0 input * PPG synchronization for output signal - OPT output is able to synchronize the edge of PPG waveform to avoid a short pulse (or glitch) appearance * Various interrupt generation causes * EI2OS supported (1) 16-bit PPG timer (x 1, not present in MB90465 series) The 16-bit PPG timer 1 is used to provide a PPG signal for waveform sequencer. (See section " PERIPHERAL RESOURCES", "6. 16-bit PPG Timer") (2) 16-bit reload timer (x 1) The 16-bit reload timer 0 is used to provide signal to waveform sequencer. (See section " RESOURCES", "5. 16-bit Reload Timer") (3) Waveform sequencer (not present in MB90465 series) By using the waveform sequencer, 16-bit PPG timer output signal can be directed to Multi-pulse generator output (OPT5 ~ 0) according to the input signal of Multi-pulse generator (SNI2 ~ 0). Meanwhile, the OPT5 ~ 0 output signal can be hardware terminated by DTTI input (DTTI1) in case of emergency. The OPT5 ~ 0 output signals are synchronized with the PPG signal in order to eliminate the unwanted glitch. (4) Register configuration
Timer Buffer Register (Upper) 15 Address: 003FFDH Read/Write Initial Value T15 R 0 14 T14 R 0 13 T13 R 0 12 T12 R 0 11 T11 R 0 10 T10 R 0 9 T09 R 0 8 T08 R 0 Bit number TMBR
PERIPHERAL
Timer Buffer Register (Lower) 7 Address: 003FFCH Read/Write Initial Value T07 R 0
6 T06 R 0
5 T05 R 0
4 T04 R 0
3 T03 R 0
2 T02 R 0
1 T01 R 0
0 T00 R 0
Bit number TMBR
Note : Register TMBR is word access only. 52
MB90460/5 Series
(Continued) Compare Clear Register (Upper) 15 14 Address: 003FFBH Read/Write Initial Value
CL15 CL14
13
CL13
12
CL12
11
CL11
10
CL10
9
CL09
8
CL08
Bit number CPCR
R/W X
R/W X 6
R/W X 5
CL05
R/W X 4
CL04
R/W X 3
CL03
R/W X 2
R/W X 1
R/W X 0
CL00
Compare Clear Register (Lower) 7 Address: 003FFAH Read/Write Initial Value
CL07
CL06
CL02
CL01
Bit number CPCR
R/W X
R/W X
R/W X
R/W X
R/W X
R/W X
R/W X
R/W X
Output Data Register (Upper) 15 14 Address: 003FF9H Read/Write Initial Value
BNKF
13
12
11
10
9
OP41
8
OP40
Bit number OPDR
RDA2 RDA1 RDA0
OP51 OP50
R 0
R 0 6
R 0 5
R 0 4
R X 3
R X 2
R X 1
R X 0 Bit number OPDR
Output Data Register (Lower) 7 Address: 003FF8H Read/Write Initial Value
OP31
OP30 OP21
OP20
OP11
OP10
OP01 OP00
R X
R X
R X
R X
R X
R X
R X
R X
Output Data Buffer Registers (Upper) 15 Addresses: 003FF7H~E1H (Odd Addresses) Read/Write Initial Value
BNKF RDA2
14
RDA1
13
RDA0
12
11
10
9
8
Bit number OPDBRB~0
_
OP51 OP50
OP41 OP40
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
Output Data Buffer Registers (Lower) 7 Addresses: 003FF6H~E0H (Even Addresses) Read/Write Initial Value
OP31
6
5
OP20
4
3
2
OP01
1
OP00
0
Bit number OPDBRB~0
OP30 OP21
OP11 OP10
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
Note : Registers CPCR, OPDR, OPDBRB~0 are word access only (Continued)
53
MB90460/5 Series
(Continued) Noise Cancellation Control Register 15 14 Address: 00008FH Read/Write Initial Value
S21 S20
13
S11
12
S10
11
S01
10
S00
9
D1
8
D0
Bit number
NCCR
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
Timer Control Status Register 7 Address: 00008EH Read/Write Initial Value
6
5
ICLR
4
ICRE
3
2
1
CLK1
0
CLK0
Bit number TCSR
TCLR MODE
TMEN CLK2
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
Input Control Register (Upper) 15 14 Address: 00008DH Read/Write Initial Value
WTS1 WTS0
13
CPIF
12
CPIE
11
10
9
8
Bit number IPCUR
CPD2 CPD1 CPD0 CMPE
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
Input Control Register (Lower) 7 Address: 00008CH Read/Write Initial Value
6
5
4
3
2
SEE2
1
0
Bit number IPCLR
CPE1 CPE0
SNC2 SNC1 SNC0
SEE1 SEE0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
Output Control Register (Upper) 14 15 Address: 00008BH Read/Write Initial Value
DTIE DTIF
13
12
11
10
9
WTIF
8
WTIE
Bit number OPCUR
NRSL OPS2
OPS1 OPS0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
Output Control Register (Lower) 7 Address: 00008AH Read/Write Initial Value
PDIF
6
PDIE
5
OPE5
4
3
2
1
0
Bit number OPCLR
OPE4 OPE3
OPE2 OPE1 OPE0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
54
MB90460/5 Series
(5) Block diagram * Block diagram of Multi-pulse generator
P12/INT2/DTTI1 P45/SNI2
Pin Pin Pin Pin Pin
DTTI SNI2
OPT5
Pin Pin Pin Pin Pin Pin
P05/OPT5 P04/OPT4
OPT4
P44/SNI1
SNI1
OPT3
P03/OPT3
P43/SNI0
SNI0
OPT2
P02/OPT2
F2MC-16LX bus
P15/INT5/TIN0
TIN0
OPT1
P01/OPT1 P00/OPT0
OPT0
Waveform sequencer 16-bit PPG timer 1
PPG1 PPG1
Interrupt #22
Interrupt #22
Interrupt #26
Interrupt #26
16-bit reload timer 0
TOUT TIN
WIN0 TIN0O Interrupt #28 Interrupt #28
Pin Pin
* : The dash line is the TIN0 path for MB90465 series. The 16-bit reload timer 0 can be used individually in MB90465 series. *
P15/INT5/TIN0 P16/INT6/TO0
(Continued)
55
MB90460/5 Series
(Continued) * Block diagram of waveform sequencer
WRITE TIMING INTERRUPT Interrupt #22 POSITION DETECTION INTERRUPT Interrupt # 26
OPCR Register
PDIRT
DTIE DTIF NRSL OPS2 OPS1 OPS0 WTIF WTIE PDIF PDIE OPE5 OPE4 OPE3 OPE2 OPE1 OPE0 From PPG1 WTS1 WTS0 P00/OPT0 P01/OPT1 P02/OPT2 P03/OPT3 P04/OPT4 P05/OPT5
OPDBRB~0 Registers
SYN Circuit Pin OPDR Register OUTPUT CONTROL CIRCUIT Pin Pin Pin Pin Pin
DTTI1 Control Circuit Noise Filter
OUTPUT DATA BUFFER REGISTER x 12
OPx1/OPx0
P12/INT2/DTTI1
Pin
D1 D0
DECODER
3
BNKF RDA2~0
3 COMPARE CLEAR INTERRUPT
F2MC-16LX bus
Pin
P15/INT5/TIN0
WTO
16-BIT TIMER
CCIRT WTIN1
P43/SNI0
Pin DATA WRITE CONTROL UNIT
OPS2 OPS1 OPS0
TIN0O WTIN0 WTIN1 WTIN1 WTO
POSITION DETECT CIRCUIT
P44/SNI1
Pin
P45/SNI2
3
SELECTOR
Pin
TIN0O
WTIN0
COMPARISON CIRCUIT
WTS1 WTS0 CPIF CPIE CPD2 CPD1 CPD0 CMPE CPE1 CPE0 SNC2 SNC1 SNC0 SEE2 SEE1 SEE0
IPCR Register
S21 S20 S11 S10 S01
COMPARE MATCH INTERRUPT
S00
D1
D0 PDIRT
Interrupt #28
NCCR Register 56
MB90460/5 Series
9. PWC Timer (x 2, PWC0 is not present in MB90465 series)
The PWC (pulse width count) timer is a 16-bit multi-functional up counter with reload timer functions and input signal pulse width count functions. The PWC timer consists of a 16-bit counter, an input pulse divider, a division ratio control register, a count input pin, a pulse output pin, and a 16-bit control register. The PWC timer has the following features: * Interrupt generated when timer overflow or end of PWC measurement. * EI2OS supported. * Timer functions : - Generates an interrupt request at set time intervals. - Outputs pulse signals synchronized with the timer cycle. - Selects the counter clock from among three internal clocks. * Pulse-width count functions: - Counts the time between external pulse input events. - Selects the counter clock from among three internal clocks. - Count mode: * H pulse width (rising edge to falling edge) / L pulse width (falling edge to rising edge) * Rising-edge cycle (rising edge to falling edge) / Falling-edge cycle (falling edge to rising edge) * Count between edges (rising or falling edge to falling or rising edge) Capable of counting cycles by dividing input pulses by 22, 24, 26, 28 using an 8-bit input divider. Generates an interrupt request upon the completion of count operation. Selects single or consecutive count operation. (1) Register configuration
Division Rate Control Register Address: ch0 00000CH ch1 00002CH Read/write Initial value PWC Data Buffer Register (Upper) 15 Address: ch0 00000BH ch1 00002BH PW15 PW14 PW13 PW12 PW11 Read/write Initial value R/W X R/W X 7 R/W X 6 R/W X 5 R/W X 4 PW10 R/W X 3 PW09 PW08 R/W X 2 R/W X 1 0 Bit number PWC0~1 14 13 12 11 10 9 8 Bit number DIV0~1 DIV1 R/W 0 DIV0 R/W 0 Bit number PWC0~1
7
6
5
4
3
2
1
0
PWC Data Buffer Register (Lower) Address: ch0 00000AH ch1 00002AH Read/write Initial value
PW07 PW06 PW05 PW04 PW03 PW02 PW01 PW00 R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X
Note : Registers PWC0 ~ 1 are word access only. (Continued)
57
MB90460/5 Series
(Continued)
PWC Control Status Register (Upper) 15 Address: ch0 000009H ch1 000029H STRT Read/write Initial value R/W 0 STOP R/W 0 7 CKS0 R/W 0 6 EDIR R 0 EDIE R/W 0 5 OVIR R/W 0 4 S/C R/W 0 OVIE R/W 0 3 2 ERR R 0 POUT R/W 0 1 0 Bit number PWCSL0~1 CKS1 R/W 0
Reserved Reserved
14
13
12
11
10
9
8
Bit number PWCSH0~1
PWC Control Status Register (Lower) Address: ch0 000008H ch1 000028H Read/write Initial value
MOD2 MOD1 MOD0 R/W 0 R/W 0 R/W 0
R/W 0
R/W 0
(3) Block diagram
PWC read 16 PWC 16 16 Write enabled Reload Data transfer 16 Overflow Clock 16-bit up count timer Timer clear F2MC-16LX bus Count enabled Control circuit
Flag setting Start edge selection Count end edge End edge selection Divider ON/OFF
Error detection
ERR
Overflow
F.F.
P07/PWO0 P23/PWO1
22 23 CKS1, CKS0, Divider clear
Clock Clock divider
Internal clock (machine clock / 4) P06/PWI0 P22/PWI1 8-bit divider
Count bit output
Count start edge
Edge detection CKS1 ERR CKS0 Division rate selection 2 DIVR
Count end interrupt request Overflow interrupt request
15
PWCS
58
MB90460/5 Series
10. UART (x 2)
The UART is a serial I/O port for asynchronous (start-stop) communication or clock-synchronous communication. The UART has the following features : * Full-duplex double buffering * Capable of asynchronous (start-stop bit) and CLK-synchronous communications * Support for the multiprocessor mode * Various method of baud rate generation : - External clock input possible - Internal clock (a clock supplied from 16-bit reload timer can be used) - Embedded dedicated baud rate generator Operation Asynchronous Baud rate 31250/9615/4808/2404/1202 bps
CLK synchronous 2 M/1 M/500 K/250 K/125 K/62.5 Kbps * : Assuming internal machine clock frequencies of 6, 8, 10, 12, and 16 MHz * Error detection functions (parity, framing, overrun) * NRZ (Non Return to Zero) signal format * Interrupt request : - Receive interrupt (receive complete, receive error detection) - Transmit interrupt (transmission complete) - Transmit / receive conforms to extended intelligent I/O service (EI2OS)
59
MB90460/5 Series
(1) Register configuration
Serial Status Register 15 Address: ch0 000023H ch1 000027H PE Read/write Initial value R 0 ORE R 0 FRE R 0 RDRF TDRE R 0 R 1 BDS R/W 0 RIE R/W 0 TIE R/W 0 14 13 12 11 10 9 8 Bit number SSR0~1
Serial Input Data Register / Serial Output Data Register 7 6 5 Address: ch0 000022H ch1 000026H D7 D6 D5 D4 Read/write Initial value Serial Control Register 15 Address: ch0 000021H ch1 000025H PEN Read/write Initial value Serial Mode Register Address: ch0 000020H ch1 000024H Read/write Initial value R/W 0 P R/W 0 7 MOD1 MOD0 R/W 0 R/W 0 SBL R/W 0 6 CS2 R/W 0 CL R/W 0 5 CS1 R/W 0 14 13 R/W X R/W X R/W X R/W X
4 D3 R/W X
3 D2 R/W X
2 D1 R/W X
1 D0 R/W X
0
Bit number SIDR0~1 / SODR0~1
12 A/D R/W 0 4 CS0 R/W 0
11 REC W 1 3 RST R/W 0
10 RXE R/W 0 2 SCKE R/W 0
9 TXE R/W 0 1 SOE R/W 0
8
Bit number SCR0~1
0
Bit number SMR0~1
Communication Prescaler Control Register 15 Address: ch0 000019H ch1 00001BH MD Read/write Initial value R/W 0
14
13
12
11 DIV2 R/W 0
10 DIV1 R/W 0
9 DIV0 R/W 0
8
Bit number CDCR0~1
60
MB90460/5 Series
(2) Block diagram
From communication prescaler Baud rate generator 16-bit reload timer P42/SCK0 External clock P40/SIN0 Clock selection circuit Transmission clock Reception clock Reception control circuit Start bit detect circuit Reception bit counter Reception parity counter End of reception Reception interrupt #39 (27H)* <#37 (25H)*> Transmission interrupt #40 (28H)* <#38 (26H)*>
Transmission control circuit Transmission start circuit Transmission bit counter Transmission parity counter
P41/SOT0
Reception status judgment circuit
Reception shifter
Transmission shifter
SIDR0/1 EI2OS reception error signal (to CPU) F2MC-16LX bus
SODR0/1
SMR0/1 register
MD1 MD0 CS2 CS1 CS0 RST SCKE SOE
SCR0/1 register
PEN P SBL CL A/D REC RXE TXE
SSR0/1 register
PE ORE FRE RDRF TDRE BDS RIE TIE Control signal
*: Interrupt number
Start of transmission Control bus
61
MB90460/5 Series
11. DTP/External Interrupts
The DTP/external interrupt circuit is activated by the signal supplied to a DTP/external interrupt pin. The CPU accepts the signal using the same procedure it uses for normal hardware interrupts and generates external interrupts or activates the extended intelligent I/O service (EI2OS). Features of DTP/External Interrupt : * Total 8 external interrupt channels. * Two request levels ("H" and "L") are provided for the intelligent I/O service. * Four request levels (rising edge, falling edge, "H" level and "L" level) are provided for external interrupt requests. (1) Register configuration
DTP/Interrupt Source Register 15 Address: 0000031H Read/write Initial value ER7 R/W 0 14 ER6 R/W 0 13 ER5 R/W 0 12 ER4 R/W 0 11 ER3 R/W 0 10 ER2 R/W 0 9 ER1 R/W 0 8 ER0 R/W 0 Bit number EIRR
DTP/Interrupt Enable Register 7 Address: 000030H Read/write Initial value EN7 R/W 0 6 EN6 R/W 0 5 EN5 R/W 0 4 EN4 R/W 0 3 EN3 R/W 0 2 EN2 R/W 0 1 EN1 R/W 0 0 EN0 R/W 0
Bit number ENIR
Request Level Setting Register (Upper) 15 Address: 0000033H Read/write Initial value LB7 R/W 0 14 LA7 R/W 0 13 LB6 R/W 0 12 LA6 R/W 0 11 LB5 R/W 0 10 LA5 R/W 0 9 LB4 R/W 0 8 LA4 R/W 0 Bit number ELVRH
Request Level Setting Register (Lower) 7 6 Address: 000032H Read/write Initial value LB3 R/W 0 LA3 R/W 0
5 LB2 R/W 0
4 LA2 R/W 0
3 LB1 R/W 0
2 LA1 R/W 0
1 LB0 R/W 0
0 LA0 R/W 0
Bit number ELVRL
62
MB90460/5 Series
(2) Block diagram
Request level setting register (ELVR)
LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0
2 2 2 2 2 2 2 2
Pin P63/INT7
Selector
Selector
Pin
P10/INT0/DTTI0
Pin P16/INT6/TO0
Selector
Selector
Pin P11/INT1
Pin
Selector
Selector
Pin P12/INT2/DTTI1
Internal data bus
P15/INT5/TIN0
Pin P14/INT4
Selector
Selector
Pin P13/INT3
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
Interrupt request number #20(14H) #22(16H) #25(19H) #27(1BH)
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
63
MB90460/5 Series
12. Delayed Interrupt Generation Module
The delayed interrupt generation module is used to generate a task switching interrupt. Interrupt requests to the F2MC-16LX CPU can be generated and cleared by software using this module. (1) Register configuration
Delayed interrupt generator module register 15 Address: 00009FH Read/write Initial value 14 13 12 11 10 9 8 R0 R/W 0 Bit number DIRR
(2) Block diagram
F2MC-16LX bus
Delayed interrupt cause issuance/cancellation decoder
Interrupt cause latch
64
MB90460/5 Series
13. A/D Converter
The converter converts the analog voltage input to an analog input pin (input voltage) to a digital value. The converter has the following features : * The minimum conversion time is 6.13 s (for a machine clock of 16 MHz; includes the sampling time). * The minimum sampling time is 3.75 s (for a machine clock of 16 MHz). * The converter uses the RC-type successive approximation conversion method with a sample and hold circuit. * A resolution of 10 bits or 8 bits can be selected. * Up to eight channels for analog input pins can be selected by a program. * Various conversion mode : - Single conversion mode : Selectively convert one channel. - Scan conversion mode : Continuously convert multiple channels. Maximum of 8 program selectable channels. - Continuous conversion mode : Repeatedly convert specified channels. - Stop conversion mode : Convert one channel then halt until the next activation (enables synchronization of the conversion start timing). * At the end of A/D conversion, an interrupt request can be generated and EIOS can be activated. * In the interrupt-enabled state, the conversion data protection function prevents any part of the data from being lost through continuous conversion. * The conversion can be activated by software, 16-bit reload timer 1 (rising edge) and 16-bit free-running timer zero detection edge. (1) Register configuration
Control Status Register (upper) 15 Address: 0000035H Read/write Initial value BUSY R/W 0 14 INT R/W 0 6 MD0 R/W 0 13 INTE R/W 0 5 ANS2 R/W 0 12 PAUS R/W 0 4 ANS1 R/W 0 11 STS1 R/W 0 3 ANS0 R/W 0 10 STS0 R/W 0 2 ANE2 R/W 0 9 STRT W 0 1 ANE1 R/W 0 0 ANE0 R/W 0 Bit number ADCS0 8
Reserved
Bit number ADCS1
Control Status Register (lower) 7 Address: 000034H Read/write Initial value A/D Data Register (upper) 15 Address: 0000037H Read/write Initial value A/D Data Register (lower) 7 Address: 000036H Read/write Initial value D7 R X S10 R/W 0 MD1 R/W 0
14 ST1 W 0
13 ST0 W 0
12 CT1 W 0
11 CT0 W 0
10
9 D9 R X
8 D8 R X
Bit number ADCR1
6 D6 R X
5 D5 R X
4 D4 R X
3 D3 R X
2 D2 R X
1 D1 R X
0 D0 R X
Bit number ADCR0
65
MB90460/5 Series
(2) Block diagram
AVCC
AVR
AVSS
D/A converter MPX AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Sample and hold circuit Input circuit
Sequential compare register
Comparator
Decoder
Data register ADCR0/1
A/D control register 0 A/D control register 1 ADCS0/1 16-bit reload timer 1 Operation clock 16-bit free-running timer zero detection Prescaler : Machine clock
66
F2MC-16LX bus
MB90460/5 Series
14. ROM Correction Function
When an address matches the value set in the address detection register, the instruction code to be loaded into the CPU is forced to be replaced with the INT9 instruction code (01H). When executing a set instruction, the CPU executes the INT9 instruction. The address match detection function is implemented by processing using the INT9 interrupt routine. The device contains two address detection registers, each provided with a compare enable bit. When the value set in the address detection register matches an address and the interrupt enable bit is "1", the instruction code to be loaded into the CPU is forced to be replaced with the INT9 instruction code. (1) Register configuration
Program Address Detection Control / Status Register 7 6 5 4 Address: 00009EH Read/write Initial value Program Address Detection Register 0 (Upper Byte) 7 Address: 001FF2H Read/write Initial value R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X 6 5 4 3 2 1 0 Bit number PADRH0 3 AD1E R/W 0 2 AD1D R/W 0 1 AD0E R/W 0 0 AD0D R/W 0 Bit number PADCSR
Program Address Detection Register 0 (Middle Byte) 15 14 13 12 Address: 001FF1H Read/write Initial value R/W X R/W X R/W X R/W X
11
10
9
8
Bit number PADRM0
R/W X
R/W X
R/W X
R/W X
Program Address Detection Register 0 (Lower Byte) 7 Address: 001FF0H Read/write Initial value R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X 6 5 4 3 2 1 0 Bit number PADRL0
(Continued)
67
MB90460/5 Series
(Continued)
Program Address Detection Register 1 (Upper Byte) 15 Address: 001FF5H Read/write Initial value R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X 14 13 12 11 10 9 8 Bit number PADRH1
Program Address Detection Register 1 (Middle Byte) 7 6 5 4 Address: 001FF4H Read/write Initial value R/W X R/W X R/W X R/W X
3
2
1
0
Bit number PADRM1
R/W X
R/W X
R/W X
R/W X
Program Address Detection Register 1 (Lower Byte) 15 14 13 12 Address: 001FF3H Read/write Initial value R/W X R/W X R/W X R/W X
11
10
9
8
Bit number PADRL1
R/W X
R/W X
R/W X
R/W X
(2) Block diagram
Address latch Comparator Address detection register 0/1 F2MC-16LX bus
INT9 command
F2MC-16LX CPU
AD0E/AD1E AD0D/AD1D
PACSR
68
MB90460/5 Series
15. ROM Mirroring Function Selection Module
The ROM mirroring function selection module can select what the FF bank allocated the ROM and sees through the 00 bank according to register settings. (1) Register configuration
ROM Mirror Function Selection Register 15 Address : 00006FH Read/write Initial value 14 13 12 11 10 9 8 M1 R/W 1 Bit number ROMM
(2) Block diagram
ROM mirroring register
F2MC-16LX bus
Address area FF bank 00 bank
ROM
69
MB90460/5 Series
16. 512/1024 Kbit Flash Memory
The 512 Kbit (MB90F462 and MB90F462A) or 1024 Kbit (MB90F463A) flash memory is allocated in the FEH to FFH banks on the CPU memory map. Like masked ROM, flash memory is read-accessible and programaccessible to the CPU using the flash memory interface circuit. The flash memory can be programmed/erased by the instruction from the CPU via the flash memory interface circuit. The flash memory can therefore be reprogrammed (updated) while still on the circuit board under integrated CPU control, allowing program code and data to be improved efficiently. Note that sector operations such as "enable sector protect" cannot be used. Features of 512/1024 Kbit flash memory * 64K words x 8 bits/32K words x 16 bits (16K+8K+8K+32K) sector configuration for MB90F462/F462A * 128K words x 8 bits/64K words x 16 bits (64K+16K+8K+8K+32K) sector configuration for MB90F463A * Automatic program algorithm (same as the Embedded Algorithm* : MBM29F400TA) * Installation of the deletion temporary stop/delete restart function * Write/delete completion detected by the data polling or toggle bit * Write/delete completion detected by the CPU interrupt * Compatibility with the JEDEC standard-type command * Each sector deletion can be executed (sectors can be freely combined) * Flash security feature * Number of write/delete operations 10,000 times guaranteed. * : Embedded Algorithm is a trademark of Advanced Micro Devices, Inc. (1) Register configuration
Flash Memory Control Status Register 7 6 Address: 0000AEH Read/write Initial value INTE RDYINT R/W 0 R/W 0 5 WE R/W 0 4 RDY R 1 3
Reserved
2 LPM1 R/W 0
1
Reserved
0 LMP0 R/W 0
Bit number FMCS
W 0
W 0
(2) Sector configuration of flash memory The flash memory has the sector configuration illustrated below. The addresses in the illustration are the upper and lower addresses of each sector. When 512 Kbit flash memory is accessed from the CPU, SA0 to SA3 are allocated in the FF bank registers.
Flash memory SA3 (16 Kbytes)
CPU address FFFFFFH FFC000H FFBFFFH FFA000H
*Writer address 7FFFFH 7C000H 7BFFFH 7A000H 79FFFH 78000H 77FFFH 70000H
SA2 (8 Kbytes)
SA1 (8 Kbytes)
FF9FFFH FF8000H
SA0 (32 Kbytes)
FF7FFFH FF0000H
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MB90460/5 Series
When 1024 Kbit flash memory is accessed from the CPU, SA0 and SA1 to SA4 are allocated in the FE and FF bank registers, respectively.
Flash memory SA4 (16 Kbytes)
CPU address FFFFFFH FFC000H FFBFFFH FFA000H
*Writer address 7FFFFH 7C000H 7BFFFH 7A000H 79FFFH 78000H 77FFFH 70000H 6FFFFH 60000H
SA3 (8 Kbytes)
SA2 (8 Kbytes)
FF9FFFH FF8000H
SA1 (32 Kbytes)
FF7FFFH FF0000H FEFFFFH FE0000H
SA0 (64 Kbytes)
* : Programmer addresses correspond to CPU addresses when data is programmed in flash memory by a parallel programmer. Programmer addresses are used to program/erase data using a general-purpose programmer.
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MB90460/5 Series
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = AVSS = 0.0 V) Parameter Symbol VCC Power supply voltage Input voltage Output voltage "L" level maximum output current "L" level average output current "L" level total maximum output current "L" level total average output current "H" level maximum output current "H" level average output current "H" level total maximum output current "H" level total average output current Power consumption Operating temperature Storage temperature AVCC AVR VI VO IOL IOLAV IOL IOLAV IOH IOHAV IOH IOHAV PD TA Tstg Rating Min. VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 -40 -55 Max. VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 15 4 100 50 -15 -4 -100 -50 300 +85 +150 Unit V V V V V mA mA mA mA mA mA mA mA mW C C Average output current = operating current x operating efficiency Average output current = operating current x operating efficiency
*3
Remarks
VCC AVCC *1 AVCC AVR, AVR AVss
*2 *2
*3 Average output current = operating current x operating efficiency
Average output current = operating current x operating efficiency
*1 : AVCC shall never exceed VCC when power-on. *2 : VI and VO shall never exceed VCC + 0.3 V. *3 : The maximum output current is a peak value for a corresponding pin. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
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MB90460/5 Series
2. Recommended Operating Conditions
(VSS = AVSS = 0.0 V) Parameter Symbol VCC VCC Smoothing capacitor Operating temperature Value Min. 3.0 4.5 3.0 Max. 5.5 5.5 5.5 Unit V V V F Remarks Normal operation (MB90462, MB90467, MB90V460) Normal operation (MB90F462, MB90F462A, MB90F463A)) Retains status at the time of operation stop Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The smoothing capacitor to be connected to the VCC pin must have a capacitance value higher than CS.
Power supply voltage
CS
0.1
1.0
TA
-40
+85
C
* C pin connection circuit
C
CS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
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MB90460/5 Series
3. DC Characteristics
(VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Parameter "H" level output voltage Symbol VOH VOL1 VOL2 VIH Pin name All output pins Condition VCC = 4.5 V, IOH = -4.0 mA Value Min. VCC - 0.5 0.7 VCC Typ. Max. 0.4 0.4 VCC + 0.3 Unit V V V V CMOS input pin CMOS hysteresis input pin Mode input pin CMOS input pin CMOS hysteresis input pin Mode pin input Remarks
"L" level output voltage
All pins except VCC = 4.5 V, P00 ~ P05 and IOL1 = 4.0 mA P30 ~ P35 P00 ~ P05 P30 ~ P35 P00 ~ P07 P30 ~ P37 P50 ~ P57 P10 ~ P17 P20 ~ P27 P40 ~ P46 P60 ~ P63 RST MD0 ~ 2 P00 ~ P07 P30 ~ P37 P50 ~ P57 P10 ~ P17 P20 ~ P27 P40 ~ P46 P60 ~ P63 RST MD0 ~ 2 All input pins VCC = 5.5 V, VSS < VI< VCC VCC = 4.5 V, IOL2 = 12.0 mA
"H" level input voltage
VIHS
0.8 VCC VCC = 3.0V ~ 5.5V (MB90462, MB90467) VCC = 4.5V ~ 5.5V (MB90F462, MB90F462A, MB90F463A)
VCC + 0.3
V
VIHM VIL
VCC - 0.3 VSS - 0.3

VCC + 0.3 0.3 VCC
V V
"L" level input voltage
VILS
VSS - 0.3
0.2 VCC
V
VILM Input leakage current IIL
VSS - 0.3 -5

VSS + 0.3 5
V A
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MB90460/5 Series
Parameter Symbol Pin name Condition VCC = 5.0 V, Internal operation at 16 MHz, Normal operation ICC Power supply current* VCC VCC = 5.0 V, Internal operation at 16 MHz, When data is written in flash mode (erasing or programming) VCC = 5.0 V, Internal operation at 16 MHz, In sleep mode VCC = 5.0 V, Internal operation at 16 MHz, In timer mode, TA = 25 C In stop mode, TA = 25 C Except AVCC, AVSS, C, VCC and VSS P00 to P07 P10 to P17 RST MD2 Value Min. Typ. 40 30 Max. 50 50 Unit mA Remarks MB90462, MB90467
MB90F462, mA MB90F462A, MB90F463A
45
60
MB90F462, mA MB90F462A, MB90F463A
ICCS
15
25
MB90462, MB90467, mA MB90F462, MB90F462A, MB90F463A MB90462, MB90467, mA MB90F462, MB90F462A, MB90F463A MB90462, MB90467, MB90F462, MB90F462A, MB90F463A
ICCT Power supply current* ICCH VCC
2.5
5.0
5
20
A
Input capacitance Pull-up resistance Pull-down resistance
CIN
10
80
pF
RUP RDOWN

25 25
50 50
100 100
k k
* : The current value is preliminary value and may be subject to change for enhanced characteristics without previous notice. The power supply current is measured with an external clock.
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MB90460/5 Series
4. AC Characteristics
(1) Clock Timings (VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Symbol Pin name Condition fC tHCYL f PWH PWL tCR tCF fCP tCP X0, X1 X0, X1 X0 X0 Value Min. 3 62.5 10 1.5 62.5 Typ. -- Max. 16 333 5 5 16 666 Unit MHz ns % ns ns Recommened duty ratio of 30% to 70% External clock operation Remarks
Parameter Clock frequency Clock cycle time Frequency fluctuation rate Input clock pulse width Input clock rise / fall time Internal operating Internal operating clock cycle time
MHz Main clock operation ns Main clock operation
*: The frequency fluctuation rate is the maximum deviation rate of the preset center frequency when the multiplied PLL signal is locked.
+ fo
f =
x 100 (%)
Center frequency
+ fo - -
tHCYL
X0
PWH tCF PWL tCR
0.8 VCC 0.2 VCC
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MB90460/5 Series
Relationship between internal operating clock frequency and power supply voltage Operation guarantee range of MB90F462, MB90F462A, MB90F463A Power supply voltage VCC (V)
5.5
4.5
3.3 3.0
Operation guarantee range of MB90462, MB90467, MB90V460
1 3 8 12
Operation guarantee range of PLL
16
Internal clock fCP (MHz) Relationship between oscillating frequency and internal operating clock frequency
Multiplied- Multiplied- Multipliedby-3 by-4 by-2 Multipliedby-1
16
Internal clock fCP (MHz)
12 9 8
Not multiplied
4
3
4
8
16
Oscillation clock fC (MHz)
The AC ratings are measured for the following measurement reference voltages
* Input signal waveform * Output signal waveform
Hysteresis input pin
0.8 VCC 0.2 VCC
Output pin
2.4 V 0.8 V
Pins other than hysteresis input/MD input
0.7 VCC 0.3 VCC
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MB90460/5 Series
(2) Reset Input Timing (VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Symbol tRSTL Pin name RST Condition Value Min. 4 tCP Max. Unit ns Remarks
Parameter Reset input time
tRSTL, tHSTL
RST
0.2 VCC 0.2 VCC
(3) Power-on Reset
(VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Symbol Pin name Condition tR tOFF VCC VCC Value Min. 0.05 4 Max. 30 Unit ms ms Due to repeated operations Remarks
Parameter Power supply rising time Power supply cut-off time
* : VCC must be kept lower than 0.2 V before power-on. Note The above values are used for causing a power-on reset. Some registers in the device are initialized only upon a power-on reset. To initialize these registers, turn the power supply using the above values.
tR
VCC
2.7 V 0.2 V 0.2 V tOFF 0.2 V
Sudden changes in the power supply voltage may cause a power-on reset. To change the power supply voltage while the device is in operation, it is recommended to raise the voltage smoothly to suppress fluctuations as shown below. In this case, change the supply voltage with the PLL clock not used. If the voltage drop is 1 V or fewer per second, however, you can use the PLL clock.
VCC 3.0 V VSS
RAM data hold
It is recommended to keep the rising speed of the supply voltage at 50 mV/ms or slower.
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MB90460/5 Series
(4) UART0 to UART1 (VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name SCK0 to SCK1 SCK0 to SCK1 SOT0 to SOT1 SCK0 to SCK1 SIN0 to SIN1 SCK0 to SCK1 SIN0 to SIN1 SCK0 to SCK1 SCK0 to SCK1 SCK0 to SCK1 SOT0 to SOT1 SCK0 to SCK1 SIN0 to SIN1 SCK0 to SCK1 SIN0 to SIN1 CL = 80 pF + 1 TTL for an output pin of external shift clock mode CL = 80 pF + 1 TTL for an output pin of internal shift clock mode Condition Value Min. 8 tCP -80 100 60 4 tCP 4 tCP 60 60 Max. 80 150 Unit Remarks ns ns ns ns ns ns ns ns ns
Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK SCK valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SOT delay time Valid SIN SCK SCK valid SIN hold time
Note : * These are AC ratings in the CLK synchronous mode. * CL is the load capacitance value connected to pins while testing. * tCP is machine cycle time (unit:ns).
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MB90460/5 Series
* Internal shift clock mode
tSCYC 2.4 V 0.8 V tSLOV 2.4 V 0.8 V
SCK
SOT
0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC
SIN
0.2 VCC
* External shift clock mode
SCK
0.2 VCC tSLOV
tSLSH 0.2 VCC
tSHSL 0.8 VCC
0.8 VCC
2.4 V
SOT
0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC
SIN
0.2 VCC
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MB90460/5 Series
(5) Resources Input Timing
(VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Pin name IN0 to IN3 SNI0 to SNI3 TIN0 to TIN1 PWI0 to PWI1 DTTI0, DTTI1 Condition Value Min. Max. Unit Remarks
Parameter
Symbol
Input pulse width
tTIWH tTIWL
4 tCP
ns
*1 : 0.7 Vcc for PWI0 input pin *2 : 0.3 Vcc for PWI0 Input pin
0.8 VCC
*1
0.8 VCC 0.2 VCC tTIWH
*2
0.2 VCC tTIWL
*2
(6) Resources Output Timing
(VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Pin name PWO0 to PWO1 PPG0 to PPG2 TO0 to TO1 Condition Value Min. 30 Max. Unit Remarks
Parameter
Symbol
CLKTOUT transition time
tTO
ns
CLK
2.4 V
tTO
2.4 V TOUT 0.8 V
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MB90460/5 Series
(8) Trigger Input Timimg
(VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Symbol tTRGH tTRGL Pin name INT0 to INT7 Condition Value Min. 5 tCP Max. Unit ns Remarks
Parameter Input pulse width
0.8 VCC
0.8 VCC 0.2 VCC tTRGH tTRGL 0.2 VCC
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MB90460/5 Series
5. A/D Converter Electrical Characteristics
(3.0 V AVR - AVSS, VCC = AVCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Parameter Resolution Symbol Non-linear error Differential linearity error Pin name Value Min. AVSS - 1.5 LSB AVSS - 3.5 LSB AVR - 3.5 LSB AVR - 6.5 LSB Typ. 10 AVSS + 0.5 LSB AVSS + 0.5 LSB AVR - 1.5 LSB AVR - 1.5 LSB Max. 3.0 5.0 2.5 1.9 AVSS + 2.5 LSB AVSS + 4.5 LSB AVR + 0.5 LSB AVR + 1.5 LSB Unit bit For MB90F462, MB90F462A, LSB MB90F463A, MB90462, MB90467 LSB For MB90V460 LSB LSB For MB90F462, MB90F462A, mV MB90F463A, MB90462, MB90467 mV For MB90V460 For MB90F462, MB90F462A, mV MB90F463A, MB90462, MB90467 mV For MB90V460 For MB90V460, MB90F462, MB90F462A, MB90F463A, MB90467. Actual value is specified as a sum of values specified in ADCR0 : CT1, CT0 and ADCR0 : ST1, ST0. Be sure that the setting value is greater than the min value Actual value is specified in ADCR0 : ST1, ST0 bits. Be sure that the setting value is greater than the min value Remarks
Total error
Zero transition voltage
VOT
AN0 to AN7
Full-scale transition voltage
VFST
AN0 to AN7
Conversion time
6.125
1000
s
Sampling period Analog port input current Analog input voltage Reference voltage
AN0 to AN7 AN0 to AN7 AVR
2
s
IAIN VAIN IA
AVSS AVSS + 2.7
2.3 2
10 AVR AVCC 6 5 5
A V V For MB90F462, MB90F462A, mA MB90F463A, MB90462, MB90467 mA For MB90V460 A *
Power supply current
AVCC
*
IAH
83
MB90460/5 Series
Parameter Symbol Pin name Value Min. Reference voltage supply current IR AVR
*
Typ. 140 600 0.9
Max. 260 900 1.3 5 4
Unit A
Remarks For MB90F462, MB90462, MB90467

A For MB90F462A, MB90F463A mA For MB90V460 A * LSB
IRH Offset between channels
--
AN0 to AN7
* : The current when the A/D converter is not operating or the CPU is in stop mode (for VCC = AVCC = AVR = 5.0 V) Note: * The error increases proportionally as |AVR - AVSS| decreases. *The output impedance of the external circuits connected to the analog inputs should be in the following range. *The output impedance of the external circuit : TBD *If the output impedance of the external circuit is too high, the sampling time might be insufficient.
C0
Comparator Analog input
C1
6. A/D Converter Glossary
Resolution : Analog changes that are identifiable with the A/D converter Linearity error : The deviation of the straight line connecting the zero transition point ("00 0000 0000" "00 0000 0001") with the full-scale transition point ("11 1111 1110" "11 1111 1111") from actual conversion characteristics Differential linearity error : The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value Total error : The total error is defined as a difference between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error and linearity error.
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MB90460/5 Series
Total error
3FF 3FE 3FD
Actual conversion value
0.5 LSB
Digital output
{1 LSB x (N - 1) + 0.5 LSB}
004 003 002 001 AVRL
(Measured value) Actual conversion value Theoretical characteristics
0.5 LSB AVRH
VNT
Analog input VNT - {1 LSB x (N - 1) + 0.5 LSB} 1 LSB AVR - AVss [V] 1024
Total error for digital output N = 1 LSB = (Theoretical value)
[LSB]
VOT(Theoretical value) = AVss + 0.5 LSB [V] VFST(Theoretical value) = AVR - 1.5 LSB [V] VNT : Voltage at a transition of digital output from (N - 1) to N
(Continued)
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MB90460/5 Series
(Continued)
Linearity error
3FF 3FE 3FD
Differential linearity error
Theoretical characteristics
N+1 VFST (Measured value)
Actual conversion value
{1 LSB x (N - 1) + VOT }
Actual conversion value
Digital output
Digital output
N
004 003 002 001 AVss
VNT (Measured value)
Actual conversion value
V(N + 1)T N-1 VNT
(Measured value) (Measured value) Actual conversion value
AVR
Theoretical characteristics VOT (Measured value)
AVR
N-2
AVss
Analog input Linearity error of = digital output N
Analog input VNT - {1 LSB x (N - 1) + VOT} 1 LSB - 1 [LSB] [V] [LSB]
Differential linearity error V (N + 1) T - VNT = 1 LSB of digital output N 1 LSB = VFST - VOT 1022
VOT : Voltage at transition of digital output from "000H" to "001H" VFST : Voltage at transition of digital output from "3FEH" to "3FFH"
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MB90460/5 Series
7. Notes on Using A/D Converter
Select the output impedance value for the external circuit of analog input according to the following conditions. Output impedance values of the external circuit of 5 k or lower are recommended. When capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor value is recommended to minimized the effect of voltage distribution between the external capacitor and internal capacitor. When the output impedance of the external circuit is too high, the sampling period for analog voltages may not be sufficient (sampling period = 4.00 s @ machine clock of 16 MHz).
* Equipment of analog input circuit model Analog input
C0
Comparator
C1
MB90462, MB90467, R 2.6 k, C 30 pF MB90V460, MB90F462, R 3.2 k, C 28 pF MB90F462A, MB90F463A Note: Listed values must be considered as standards.
* Error
The smaller the | AVR - AVSS |, the greater the error would become relatively.
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MB90460/5 Series
EXAMPLE CHARACTERISTICS
* Power suppy current of MB90462/467
ICC[mA] 40.00 35.00 30.00 25.00 20.00 15.00 10.00 5.00 0.00 0.0 1.0 2.0
ICCS[mA] 20.00 fc=16[MHz] 18.00 16.00 fc=12[MHz] fc=10[MHz] fc= 8[MHz] 14.00 12.00 10.00 8.00 6.00 fc= 4[MHz] 4.00 fc= 2[MHz]
2.00 0.00 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 Vcc[V]
3.0
4.0
5.0
6.0
7.0
Vcc[V] 8.0
ICCH[uA] 10.00 9.00 8.00 7.00 6.00 5.00 4.00 3.00 2.00 1.00 0.00 0.0 1.0 2.0
TA=25[o ]
fc=32[kHz]
3.0
4.0
5.0
6.0
7.0
Vcc[V] 8.0
88
C
T A=25[oC]
TA=25[o ]
fc=16[MHz]
fc=12[MHz] fc=10[MHz] fc= 8[MHz]
fc= 4[MHz] fc= 2[MHz]
C
(Continued)
MB90460/5 Series
(Continued)
* Output voltage of MB90462/467
Vcc-VOH[V] 3.00
VOL1[mV] 2000 1800
2.50 Vcc=3.0[V] 2.00 Vcc=4.0[V] 1.50 Vcc=4.5[V] Vcc=5.0[V] Vcc=5.5[V] Vcc=6.0[V] Vcc=3.5[V]
1600 Vcc=4.5[V] 1400 1200 1000 800 600 400 200 Vcc=3.0[V] Vcc=5.0[V] Vcc=5.5[V] Vcc=6.0[V]
1.00
0.50
0.00 0.0 -5.0 -10.0 -15.0 -20.0
IOH[mA] -25.0
0 0.0 5.0 10.0 15.0 20.0
VOL2[mV] 1000 900 800 700 600 500 400 300 200 100 0 0.0 5.0
TA=25[o ]
Vcc=3.0[V] Vcc=3.5[V] Vcc=4.0[V] Vcc=4.5[V] Vcc=5.0[V] Vcc=5.5[V] Vcc=6.0[V]
10.0
15.0
20.0
IOL2[mA] 25.0
C
TA=25[o ]
TA=25[o ]
Vcc=4.0[V] Vcc=3.5[V]
C
C
IOL1[mA 25.0
(Continued)
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MB90460/5 Series
(Continued)
* Power suppy current of MB90F462
ICC[mA] 35.00
ICCS[mA] 20.00 fc=16[MHz] 18.00
30.00 16.00 25.00 fc=12[MHz] fc=10[MHz] fc= 8[MHz] 15.00 14.00 12.00 10.00 8.00 6.00 fc= 4[MHz] 4.00 5.00 fc= 2[MHz] 2.00 0.00 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 fc= 4[MHz] fc= 2[MHz] fc=12[MHz] fc=10[MHz] fc= 8[MHz] fc=16[MHz]
20.00
10.00
0.00 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0
Vcc[V] 8.0
ICCH[ A ] 10.00 9.00 8.00 7.00 6.00 5.00 4.00 3.00 2.00 1.00 0.00 0.0 1.0 2.0
u
TA=25[o ]
fc=32[kHz]
3.0
4.0
5.0
6.0
7.0
Vcc[V] 8.0
90
C
T A=25[o ]
TA=25[o ]
C
C
Vcc[V]
(Continued)
MB90460/5 Series
(Continued)
* Output voltage of MB90F462
Vcc-VOH[V] 3.00
VOL1[mV] 5.00 4.50
2.50
Vcc=3.0[V] 4.00 Vcc=3.5[V] 3.50 3.00 Vcc=3.0[V]
2.00
1.50
1.00
Vcc=4.0[V] Vcc=4.5[V] Vcc=5.0[V] Vcc=5.5[V] Vcc=6.0[V]
2.50 2.00 1.50 Vcc=4.5[V] Vcc=5.0[V] Vcc=5.5[V] Vcc=6.0[V]
0.50
1.00 0.50
0.00 0.0 -5.0 -10.0 -15.0 -20.0
IOH[mA] -25.0
0.00 0.0 5.0 10.0 15.0 20.0
VOL2[mV] 1000 900 800 700
TA=25[o ]
Vcc=3.0[V] 600 500 400 300 200 100 0 0.0 5.0 10.0 15.0 20.0 IOL2[mA] 25.0 Vcc=3.5[V] Vcc=4.0[V] Vcc=4.5[V] Vcc=5.0[V] Vcc=5.5[V] Vcc=6.0[V]
C
TA=25[o ]
TA=25[o ]
C
C
Vcc=4.0[V] Vcc=3.5[V]
IOL1[mA 25.0
(Continued)
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MB90460/5 Series
(Continued)
* Power supply current of MB90F462A/F463A
TA=25[ ] TA=25[ ]
30.0 25.0 20.0 15.0
ICC [mA]
ICCS [mA]
14.0
FCH =16.0[MHz]
12.0 10.0
FCH =16.0[MHz]
FCH =12.0[MHz]
FCH =12.0[MHz]
8.0
FCH =8.0[MHz]
6.0 4.0
FCH =8.0[MHz]
10.0
FCH =4.0[MHz]
FCH =4.0[MHz]
5.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0
FCH =2.0[MHz]
2.0 0.0 2.0 3.0 4.0 5.0 6.0
FCH =2.0[MHz]
7.0Vcc[V]
7.0 Vcc[V]
ICCH [A]
TA=25[ ]
5.0
4.0
3.0
FCH= 32.0[MHz]
2.0
1.0
0.0 2.0 3.0 4.0 5.0 6.0 7.0 Vcc[V]
(Continued)
92
MB90460/5 Series
* Output voltage of MB90F462A/F463A
TA=25[ ] Vcc=3.5[V] Vcc=4.0[V] 1.0 Vcc=4.5[V] Vcc=5.0[V] 0.8 Vcc=5.5[V] Vcc=6.0[V] 0.6 Vcc=4. Vcc=4.5[V] Vcc=5.0[V] Vcc=5.5[V] 0.6 0.4 Vcc=6.0[V] TA=25[ ] Vcc=3.0[V]
1.2
VCC-VOH [V]
VOL1 [V] 0.8
Vcc=3.5[V]
0.4 0.2 0.2
0.0 0 -2 -4 -6 -8 -10 IOH
0.0 0 2 4 6 8 10 IOL [mA]
VOL2 [V] 0.25
TA=25[ ] Vcc=3.0[V]
Vcc=3.5[V] 0.20 Vcc=4.0[V] Vcc=4.5[V] Vcc=5.0[V] 0.15 Vcc=5.5[V] Vcc=6.0[V]
0.10
0.05
0.00 0 2 4 6 8 10 IOL [mA]
93
MB90460/5 Series
ORDERING INFORMATION
Part number MB90F462PFM-G MB90F462APFM-G MB90F463APFM-G MB90462PFM-G-XXX MB90467PFM-G-XXX MB90F462PF-G MB90F462APF-G MB90F463APF-G MB90462PF-G-XXX MB90467PF-G-XXX MB90F462P-G-SH MB90F462AP-G-SH MB90F463AP-G-SH MB90462P-G-XXX-SH MB90467P-G-XXX-SH Package Remarks
64-pin Plastic LQFP (FPT-64P-M09)
64-pin Plastic QFP (FPT-64P-M06)
64-pin Plastic SH-DIP (DIP-64P-M01)
Note : XXX is the internal reference number for ROM code release.
94
MB90460/5 Series
PACKAGE DIMENSIONS
64-pin plastic QFP (FPT-64P-M06)
24.700.40(.972.016) 20.000.20(.787.008)
51 33
0.170.06 (.007.002)
52
32
18.700.40 (.736.016) 14.000.20 (.551.008) INDEX Details of "A" part 3.00 -0.20 .118 -.008
20
+0.35 +.014
(Mounting height)
64
0~8
1 19
1.00(.039)
0.420.08 (.017.003)
0.20(.008)
M
0.25 -0.20 1.200.20 (.047.008)
+0.15 +.006
.010 -.008 (Stand off)
"A" 0.10(.004)
(c) 2001 FUJITSU LIMITED F64013S-c-4-4
Dimensions in mm (inches) (Continued)
95
MB90460/5 Series
(Continued) 64-pin plastic LQFP (FPT-64P-M09)
14.000.20(.551.008)SQ 12.000.10(.472.004)SQ
48 33
0.1450.055 (.0057.0022)
49
32
0.10(.004) Details of "A" part 1.50 -0.10 .059 -.004
+0.20 +.008
(Mounting height)
0.25(.010) INDEX 0~8
64 17
1
16
"A"
0.65(.026)
0.320.05 (.013.002)
0.500.20 (.020.008) 0.600.15 (.024.006)
0.100.10 (.004.004) (Stand off)
0.13(.005)
M
(c) 2001 FUJITSU LIMITED F64018S-c-2-4
Dimensions in mm (inches) (Continued)
96
MB90460/5 Series
(Continued) 64-pin plastic SH-DIP (DIP-64P-M01)
58.00 -0.55 2.283 -.022
+0.22
+.009
INDEX-1 17.000.25 (.669.010) INDEX-2
4.95 -0.20 .195 -.008
+0.70 +.028
0.70 -0.19 .028 -.007
+0.50 +.020
3.30 -0.30 .130
+0.20 +.008 -.012 +0.40 -0.20 +.016 -.008
0.270.10 (.011.004) 1.378 .0543 1.778(.0700) 0.470.10 (.019.004) 0.25(.010)
M
19.05(.750) 0~15
1.00 -0
+0.50 +.020
.039 -.0
(c) 2001 FUJITSU LIMITED D64001S-c-4-5
Dimensions in mm (inches)
97
MB90460/5 Series
FUJITSU LIMITED
For further information please contact: Japan FUJITSU LIMITED Marketing Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3353 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fme.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-6281-0770 Fax: +65-6281-0220 http://www.fmal.fujitsu.com/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://www.fmk.fujitsu.com/ F0208 FUJITSU LIMITED Printed in Japan
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.

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